Patents by Inventor Bernd Nerz
Bernd Nerz has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 10235138Abstract: An instruction configured to perform a plurality of functions is executed. Based on a function code associated with the instruction having a selected value, one or more inputs of the instruction are checked to determine which one or more functions of the plurality of functions are to be performed. Based on a first input of the one or more inputs having a first value, a function of providing raw entropy is performed, in which the providing of raw entropy includes storing a number of raw random numbers. Further, based on a second input of the one or more inputs having a second value, a function of providing conditioned entropy is provided, in which the providing of conditioned entropy includes storing a number of conditioned random numbers.Type: GrantFiled: September 30, 2016Date of Patent: March 19, 2019Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Dan F. Greiner, Bernd Nerz, Timothy J. Slegel, Tamas Visegrady, Christian Zoellin
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Patent number: 10223300Abstract: Input/output (I/O) operation requests from pageable storage mode guests are interpreted without host intervention. In a pageable mode virtual environment, requests issued by pageable storage mode guests are processed by one or more processors of the environment absent intervention from one or more hosts of the environment. Processing of the requests includes manipulating, by at least one processor on behalf of the guests, buffer state information stored in host storage. The manipulating is performed via instructions initiated by the guests and processed by one or more of the processors.Type: GrantFiled: April 19, 2016Date of Patent: March 5, 2019Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Janet R. Easton, William A. Holder, Bernd Nerz, Damian L. Osisek, Gustav E. Sittmann, III, Richard P. Tarcza, Leslie W. Wyman
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Publication number: 20190065203Abstract: A machine instruction is provided that includes an opcode field to provide an opcode, the opcode to identify a perform pseudorandom number operation, and a register field to be used to identify a register, the register to specify a location in memory of a first operand to be used. The machine instruction is executed, and execution includes for each block of memory of one or more blocks of memory of the first operand, generating a hash value using a 512 bit secure hash technique and at least one seed value of a parameter block of the machine instruction; and storing at least a portion of the generated hash value in a corresponding block of memory of the first operand, the generated hash value being at least a portion of a pseudorandom number.Type: ApplicationFiled: October 25, 2018Publication date: February 28, 2019Inventors: Dan F. Greiner, Bernd Nerz, Tamas Visegrady
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Patent number: 10133575Abstract: A machine instruction is provided that includes an opcode field to provide an opcode, the opcode to identify a perform pseudorandom number operation, and a register field to be used to identify a register, the register to specify a location in memory of a first operand to be used. The machine instruction is executed, and execution includes for each block of memory of one or more blocks of memory of the first operand, generating a hash value using a 512 bit secure hash technique and at least one seed value of a parameter block of the machine instruction; and storing at least a portion of the generated hash value in a corresponding block of memory of the first operand, the generated hash value being at least a portion of a pseudorandom number.Type: GrantFiled: May 24, 2018Date of Patent: November 20, 2018Assignee: International Business Machines CorporationInventors: Dan F. Greiner, Bernd Nerz, Tamas Visegrady
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Publication number: 20180275992Abstract: A machine instruction is provided that includes an opcode field to provide an opcode, the opcode to identify a perform pseudorandom number operation, and a register field to be used to identify a register, the register to specify a location in memory of a first operand to be used. The machine instruction is executed, and execution includes for each block of memory of one or more blocks of memory of the first operand, generating a hash value using a 512 bit secure hash technique and at least one seed value of a parameter block of the machine instruction; and storing at least a portion of the generated hash value in a corresponding block of memory of the first operand, the generated hash value being at least a portion of a pseudorandom number.Type: ApplicationFiled: May 24, 2018Publication date: September 27, 2018Inventors: Dan F. Greiner, Bernd Nerz, Tamas Visegrady
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Patent number: 10061585Abstract: A machine instruction is provided that includes an opcode field to provide an opcode, the opcode to identify a perform pseudorandom number operation, and a register field to be used to identify a register, the register to specify a location in memory of a first operand to be used. The machine instruction is executed, and execution includes for each block of memory of one or more blocks of memory of the first operand, generating a hash value using a 512 bit secure hash technique and at least one seed value of a parameter block of the machine instruction; and storing at least a portion of the generated hash value in a corresponding block of memory of the first operand, the generated hash value being at least a portion of a pseudorandom number.Type: GrantFiled: January 28, 2016Date of Patent: August 28, 2018Assignee: International Business Machines CorporationInventors: Dan F. Greiner, Bernd Nerz, Tamas Visegrady
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Publication number: 20180095729Abstract: An instruction configured to perform a plurality of functions is executed. Based on a function code associated with the instruction having a selected value, one or more inputs of the instruction are checked to determine which one or more functions of the plurality of functions are to be performed. Based on a first input of the one or more inputs having a first value, a function of providing raw entropy is performed, in which the providing of raw entropy includes storing a number of raw random numbers. Further, based on a second input of the one or more inputs having a second value, a function of providing conditioned entropy is provided, in which the providing of conditioned entropy includes storing a number of conditioned random numbers.Type: ApplicationFiled: September 30, 2016Publication date: April 5, 2018Inventors: Dan F. Greiner, Bernd Nerz, Timothy J. Slegel, Tamas Visegrady, Christian Zoellin
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Publication number: 20180097619Abstract: A machine instruction is provided that has associated therewith an opcode to identify a perform pseudorandom number operation, and an operand to be used by the machine instruction. The machine instruction is executed, and execution includes obtaining a modifier indicator. Based on the modifier indicator having a first value, performing a deterministic pseudorandom number seed operation, which includes obtaining seed material based on information stored in the second operand. A selected hash technique and the seed material are used to provide one or more seed values, and the one or more seed values are stored in a parameter block.Type: ApplicationFiled: November 21, 2017Publication date: April 5, 2018Inventors: Dan F. GREINER, Bernd NERZ, Tamas VISEGRADY
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Patent number: 9898348Abstract: A processor determines that processing of a thread is suspended due to limited availability of a processing resource. The processor supports execution of the plurality of threads in parallel. The processor obtains a lock on a second processing resource that is substitutable as a resource during processing of the first thread. The second processing resource is included as part of a component that is external to the processor. The component supports a number of threads that is less than the plurality of threads. The processing of the thread is suspended until the lock is available. The processor processes the first thread using the second processing resource. The processor includes a shared register to support mapping a portion of the plurality of threads to the component. The portion of the plurality of threads is equal to, at most, the number of threads supported by component.Type: GrantFiled: October 22, 2014Date of Patent: February 20, 2018Assignee: International Business Machines CorporationInventors: Khary J. Alexander, Markus Helms, Christian Jacobi, Bernd Nerz, Volker Urban
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Patent number: 9886327Abstract: A processor determines that processing of a thread is suspended due to limited availability of a processing resource. The processor supports execution of the plurality of threads in parallel. The processor obtains a lock on a second processing resource that is substitutable as a resource during processing of the first thread. The second processing resource is included as part of a component that is external to the processor. The component supports a number of threads that is less than the plurality of threads. The processing of the thread is suspended until the lock is available. The processor processes the first thread using the second processing resource. The processor includes a shared register to support mapping a portion of the plurality of threads to the component. The portion of the plurality of threads is equal to, at most, the number of threads supported by component.Type: GrantFiled: November 30, 2015Date of Patent: February 6, 2018Assignee: International Business Machines CorporationInventors: Khary J. Alexander, Markus Helms, Christian Jacobi, Bernd Nerz, Volker Urban
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Patent number: 9860056Abstract: A machine instruction is provided that has associated therewith an opcode to identify a perform pseudorandom number operation, and an operand to be used by the machine instruction. The machine instruction is executed, and execution includes obtaining a modifier indicator. Based on the modifier indicator having a first value, performing a deterministic pseudorandom number seed operation, which includes obtaining seed material based on information stored in the second operand. A selected hash technique and the seed material are used to provide one or more seed values, and the one or more seed values are stored in a parameter block.Type: GrantFiled: August 16, 2016Date of Patent: January 2, 2018Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Dan F. Greiner, Bernd Nerz, Tamas Visegrady
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Patent number: 9760511Abstract: A system and method of implementing a modified priority routing of an input/output (I/O) interruption. The system and method determines whether the I/O interruption is pending for a core and whether any of a plurality of guest threads of the core is enabled for guest thread processing of the interruption in accordance with the determining that the I/O interruption is pending. Further, the system and method determines whether at least one of the plurality of guest threads enabled for guest thread processing is in a wait state and, in accordance with the determining that the at least one of the plurality of guest threads enabled for guest thread processing is in the wait state, routes the I/O interruption to a guest thread enabled for guest thread processing and in the wait state.Type: GrantFiled: October 8, 2014Date of Patent: September 12, 2017Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Jonathan D. Bradbury, Fadi Y. Busaba, Mark S. Farrell, Charles W. Gainey, Jr., Dan F. Greiner, Lisa C. Heller, Christian Jacobi, Jeffrey P. Kubala, Frank Lehnert, Bernd Nerz, Damian L. Osisek, Donald W. Schmidt, Timothy J. Slegel
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Publication number: 20170041135Abstract: A machine instruction is provided that has associated therewith an opcode to identify a perform pseudorandom number operation, and an operand to be used by the machine instruction. The machine instruction is executed, and execution includes obtaining a modifier indicator. Based on the modifier indicator having a first value, performing a deterministic pseudorandom number seed operation, which includes obtaining seed material based on information stored in the second operand. A selected hash technique and the seed material are used to provide one or more seed values, and the one or more seed values are stored in a parameter block.Type: ApplicationFiled: August 16, 2016Publication date: February 9, 2017Inventors: Dan F. Greiner, Bernd Nerz, Tamas Visegrady
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Patent number: 9424000Abstract: A machine instruction is provided that includes an opcode field to provide an opcode, the opcode to identify a perform pseudorandom number operation, and a register field to be used to identify a register, the register to specify a location in memory of a second operand to be used. The machine instruction is executed, and execution includes obtaining a modifier field of a register associated with the machine instruction; based on the modifier field having a first value, performing a deterministic pseudorandom number seed operation, which includes obtaining seed material based on information stored in the second operand; using a 512 bit secure hash technique and the seed material to provide one or more seed values; and storing the one or more seed values in a parameter block.Type: GrantFiled: November 22, 2014Date of Patent: August 23, 2016Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Dan F. Greiner, Bernd Nerz, Tamas Visegrady
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Publication number: 20160232113Abstract: Input/output (I/O) operation requests from pageable storage mode guests are interpreted without host intervention. In a pageable mode virtual environment, requests issued by pageable storage mode guests are processed by one or more processors of the environment absent intervention from one or more hosts of the environment. Processing of the requests includes manipulating, by at least one processor on behalf of the guests, buffer state information stored in host storage. The manipulating is performed via instructions initiated by the guests and processed by one or more of the processors.Type: ApplicationFiled: April 19, 2016Publication date: August 11, 2016Inventors: Janet R. Easton, William A. Holder, Bernd Nerz, Damian L. Osisek, Gustav E. Sittmann, III, Richard P. Tarcza, Leslie W. Wyman
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Publication number: 20160202984Abstract: A machine instruction is provided that includes an opcode field to provide an opcode, the opcode to identify a perform pseudorandom number operation, and a register field to be used to identify a register, the register to specify a location in memory of a first operand to be used. The machine instruction is executed, and execution includes for each block of memory of one or more blocks of memory of the first operand, generating a hash value using a 512 bit secure hash technique and at least one seed value of a parameter block of the machine instruction; and storing at least a portion of the generated hash value in a corresponding block of memory of the first operand, the generated hash value being at least a portion of a pseudorandom number.Type: ApplicationFiled: January 28, 2016Publication date: July 14, 2016Inventors: Dan F. Greiner, Bernd Nerz, Tamas Visegrady
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Publication number: 20160117200Abstract: A processor determines that processing of a thread is suspended due to limited availability of a processing resource. The processor supports execution of the plurality of threads in parallel. The processor obtains a lock on a second processing resource that is substitutable as a resource during processing of the first thread. The second processing resource is included as part of a component that is external to the processor. The component supports a number of threads that is less than the plurality of threads. The processing of the thread is suspended until the lock is available. The processor processes the first thread using the second processing resource. The processor includes a shared register to support mapping a portion of the plurality of threads to the component. The portion of the plurality of threads is equal to, at most, the number of threads supported by component.Type: ApplicationFiled: November 30, 2015Publication date: April 28, 2016Inventors: Khary J. Alexander, Markus Helms, Christian Jacobi, Bernd Nerz, Volker Urban
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Publication number: 20160117193Abstract: A processor determines that processing of a thread is suspended due to limited availability of a processing resource. The processor supports execution of the plurality of threads in parallel. The processor obtains a lock on a second processing resource that is substitutable as a resource during processing of the first thread. The second processing resource is included as part of a component that is external to the processor. The component supports a number of threads that is less than the plurality of threads. The processing of the thread is suspended until the lock is available. The processor processes the first thread using the second processing resource. The processor includes a shared register to support mapping a portion of the plurality of threads to the component. The portion of the plurality of threads is equal to, at most, the number of threads supported by component.Type: ApplicationFiled: October 22, 2014Publication date: April 28, 2016Inventors: Khary J. Alexander, Markus Helms, Christian Jacobi, Bernd Nerz, Volker Urban
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Patent number: 9323560Abstract: Input/output (I/O) operation requests from pageable storage mode guests are interpreted without host intervention. In a pageable mode virtual environment, requests issued by pageable storage mode guests are processed by one or more processors of the environment absent intervention from one or more hosts of the environment. Processing of the requests includes manipulating, by at least one processor on behalf of the guests, buffer state information stored in host storage. The manipulating is performed via instructions initiated by the guests and processed by one or more of the processors.Type: GrantFiled: July 20, 2015Date of Patent: April 26, 2016Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Janet R. Easton, William A. Holder, Bernd Nerz, Damian L. Osisek, Gustav E. Sittman, III, Richard P. Tarcza, Leslie W. Wyman
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Publication number: 20160103774Abstract: A system and method of implementing a modified priority routing of an input/output (I/O) interruption. The system and method determines whether the I/O interruption is pending for a core and whether any of a plurality of guest threads of the core is enabled for guest thread processing of the interruption in accordance with the determining that the I/O interruption is pending. Further, the system and method determines whether at least one of the plurality of guest threads enabled for guest thread processing is in a wait state and, in accordance with the determining that the at least one of the plurality of guest threads enabled for guest thread processing is in the wait state, routes the I/O interruption to a guest thread enabled for guest thread processing and in the wait state.Type: ApplicationFiled: October 8, 2014Publication date: April 14, 2016Inventors: Jonathan D. Bradbury, Fadi Y. Busaba, Mark S. Farrell, Charles W. Gainey, JR., Dan F. Greiner, Lisa C. Heller, Christian Jacobi, Jeffrey P. Kubala, Frank Lehnert, Bernd Nerz, Damian L. Osisek, Donald W. Schmidt, Timothy J. Slegel