Abstract: A symbol clock (16) associated with a symbol stream (5) in a synchronized communication receiver can be recovered by adjusting the phase of a symbol clock signal (12). The phase adjustment is accomplished by applying a digitally controlled delay (13) to the symbol clock signal based on a timing relationship between the symbol clock and symbol transitions (17) in the symbol stream.

Abstract: A hardware control loop (19) derives an AGC setting for a communication receiver based on signal strength information (16), without incurring program execution delay of a baseband processor.

Abstract: All-digital FSK demodulation can be accomplished by producing in response to a received IF signal digital information (22) indicative of a frequency of the IF signal. A symbol represented by the IF signal can then be determined (28, 44) in response to the digital information.

Abstract: A phase-locked loop (10) comprises a voltage-controlled oscillator (12) to which a control voltage is applied as produced by a phase/frequency detector (22) as a function of the difference between the frequency (fref) of a reference signal and the output frequency (fvco) of the voltage controlled oscillator (12) and the oscillator contains as a frequency-influencing circuit element a varactor (14) whose capacitance value can be varied over a fine adjustment range by the control voltage for altering the output frequency. A variable capacitance (18) is provided which can be connected in parallel to the varactor (14) when there is a change in the frequency (fref) of the reference signal, the value of this capacitance (18) being adjustable as a function of the control voltage output by the phase/frequency detector (22).

Abstract: A symbol clock (16) associated with a symbol stream (5) in a synchronized communication receiver can be recovered by adjusting the phase of a symbol clock signal (12). The phase adjustment is accomplished by applying a digitally controlled delay (13) to the symbol clock signal based on a timing relationship between the symbol clock and symbol transitions (17) in the symbol stream.

Abstract: A hardware control loop (19) derives an AGC setting for a communication receiver based on signal strength information (16), without incurring program execution delay of a baseband processor.

Abstract: A phase-locked loop (10) comprises a voltage-controlled oscillator (12) to which a control voltage is applied as produced by a phase/frequency detector (22) as a function of the difference between the frequency (fref) of a reference signal and the output frequency (fvco) of the voltage controlled oscillator (12) and the oscillator contains as a frequency-influencing circuit element a varactor (14) whose capacitance value can be varied over a fine adjustment range by the control voltage for altering the output frequency. A variable capacitance (18) is provided which can be connected in parallel to the varactor (14) when there is a change in the frequency (fref) of the reference signal, the value of this capacitance (18) being adjustable as a function of the control voltage output by the phase/frequency detector (22).

Abstract: All-digital FSK demodulation can be accomplished by producing in response to a received IF signal digital information (22) indicative of a frequency of the IF signal. A symbol represented by the IF signal can then be determined (28, 44) in response to the digital information.