Abstract: A package for mounting on a mounting base is disclosed. In one example, the package comprises a carrier, an electronic component mounted at the carrier, leads electrically coupled with the electronic component and to be electrically coupled with the mounting base, and a linear spacer for defining a spacing with respect to the carrier.

Abstract: A package is disclosed. In one example, the package includes a first main face for mounting a heat sink and an opposing second main face for being mounted on a mounting base. The package comprises a carrier, an electronic component mounted at the carrier, and an encapsulant encapsulating at least part of the electronic component and at least part of the carrier. Electrically insulating material covers electrically conductive material of the carrier at said first main face. The encapsulant comprises at least one step at the first main face.

Abstract: A package is disclosed. In one example, the package includes a first main face for mounting a heat sink and an opposing second main face for being mounted on a mounting base. The package comprises a carrier, an electronic component mounted at the carrier, and an encapsulant encapsulating at least part of the electronic component and at least part of the carrier. Electrically insulating material covers electrically conductive material of the carrier at said first main face. The encapsulant comprises at least one step at the first main face.

Abstract: A semiconductor package comprises a semiconductor transistor circuit comprising a semiconductor transistor die comprising die terminals, including a collector/drain, a source/emitter, a sense source/sense emitter, a gate, and a load path, a driver line connected with the gate, and a gate control loop in which the a sense source/sense emitter is connected with the driver line, a plurality of external contacts comprising at least one first external contact connected with the drain/collector, at least one second external contact connected with the source/emitter, a third external contact connected with the a sense source/sense emitter, and a fourth external contact connected with the gate, wherein the plurality of external contacts are arranged or configured to reduce or utilize the magnetic coupling induced by a load current flowing through the load path.

Abstract: An electronic device module includes: a core layer having an opening; an electronic device disposed in the opening, one or both of the core layer and the electronic device being at least partially covered by an adhesion promoter layer; and an encapsulant layer at least partially embedding the core layer and the electronic device.

Abstract: A method for fabricating a semiconductor device module includes: providing a first encapsulant layer and a core layer disposed on the first encapsulant layer, the core layer having an opening; disposing a semiconductor device in the opening, the semiconductor device having a die carrier and a semiconductor die disposed on the die carrier; dispensing an encapsulant onto the semiconductor device; applying a second polymer layer onto the encapsulant so that the encapsulant is pressed into the opening; and laminating together the first and second encapsulant layers and the encapsulant.

Abstract: A semiconductor package is disclosed. In one example, the semiconductor package comprises a package body and a second die pad at least partially encapsulated in the package body. A first semiconductor die is at least partially encapsulated in the package body and arranged on the first die pad. A further device at least partially encapsulated in the package body and arranged on the second die pad. At least one first lead is connected with the first contact pad of the first semiconductor die. At least one second lead is connected with the second contact pad of the further device. An electrical conductor is connected between the at least one first lead and the at least one second lead, the electrical conductor being completely encapsulated in the package body.

Abstract: A semiconductor package is disclosed. In one example, the semiconductor package includes a package body. A first diepad is at least partially uncovered by the package body at the first main surface. A second diepad is at least partially uncovered by the package body at the first main surface. A first semiconductor chip is arranged on the first diepad. A second semiconductor chip is arranged on the second diepad. The semiconductor package further includes at least one lead protruding out of the package body at the side surface. A first groove is formed in the first main surface, wherein the first groove is arranged between the first diepad and the second diepad, and a second groove is formed in the first main surface, wherein the second groove is arranged between the at least one lead and at least one of the first diepad and the second diepad.

Abstract: A semiconductor package includes: a die carrier having a first main face and a second main face opposite to the first main face; a semiconductor die disposed on the die carrier, the semiconductor die including a first pad and a second pad; a first electrical connector disposed on the first pad; an encapsulant at least partially covering the semiconductor die, the die carrier, and the first electrical connector; and an insulation layer disposed on the second main face of the die carrier.

Abstract: A semiconductor package includes a first die pad, a first semiconductor die mounted on the first die pad, an encapsulant body of electrically insulating material that encapsulates first die pad and the first semiconductor die, a plurality of package leads that each protrude out of a first outer face of the encapsulant body, a connection lug that protrudes out of a second outer face of the encapsulant body, the second outer face being opposite from the first outer face. The first semiconductor die includes first and second voltage blocking terminals. The connection lug is electrically connected to one of the first and second voltage blocking terminals of the first semiconductor die. A first one of the package leads is electrically connected to an opposite one of the first and second voltage blocking terminals of the first semiconductor die that the first connection lug is electrically connected to.

Abstract: A stacked module arrangement includes: a first molded electronic module; a second molded electronic module; and an interface by which the first molded electronic module and the second molded electronic module are physically and electrically connected to one another in a stacked configuration. The first molded electronic module is a power electronic module having a maximum breakdown voltage of at least 40 V and a maximum DC current of at least 10 A.

Abstract: A semiconductor assembly includes a laminate substrate that includes a plurality of laminate layers of electrically insulating material stacked on top of one another, a semiconductor package that includes a package body of electrically insulating encapsulant material and a plurality of electrical contacts that are exposed from the package body, wherein the semiconductor package is embedded within the laminate layers of the laminate substrate, wherein the semiconductor package comprises a delamination mitigation feature, wherein the delamination mitigation feature comprises one or both of a macrostructure that engages with the laminate layers, and a roughened surface of microstructures that enhances adhesion between the semiconductor package and the laminate layers.

Abstract: A semiconductor package comprising a substrate, at least one semiconductor die disposed on the substrate, at least one electrical connector connected with the semiconductor die, an encapsulant covering the substrate, the at least one semiconductor die, and at least partially the electrical connector, the encapsulant comprising a recess formed into a main surface of the encapsulant, wherein the at least one electrical connector is exposed within the recess.

Abstract: A method includes providing a first lead frame that includes a first die pad and a first row of leads, providing a connection lug, mounting a first semiconductor die on the first die pad, the first semiconductor die including first and second voltage blocking terminals, electrically connecting the connection lug to one of the first and second voltage blocking terminals, electrically connecting a first one of the leads from the first row to an opposite one of the first and second voltage blocking terminals, and forming an encapsulant body of electrically insulating material that encapsulates first die pad and the first semiconductor die. After forming the encapsulant body, the first row of leads each protrude out of a first outer face of the encapsulant body and the connection lug protrudes out of a second outer face of the encapsulant body.

Abstract: A semiconductor package includes a first die pad, a first semiconductor die mounted on the first die pad, an encapsulant body of electrically insulating material that encapsulates first die pad and the first semiconductor die, a plurality of package leads that each protrude out of a first outer face of the encapsulant body, a connection lug that protrudes out of a second outer face of the encapsulant body, the second outer face being opposite from the first outer face. The first semiconductor die includes first and second voltage blocking terminals. The connection lug is electrically connected to one of the first and second voltage blocking terminals of the first semiconductor die. A first one of the package leads is electrically connected to an opposite one of the first and second voltage blocking terminals of the first semiconductor die that the first connection lug is electrically connected to.

Abstract: A package is disclosed. In one example, the package includes a first main face for mounting a heat sink and an opposing second main face for being mounted on a mounting base. The package comprises a carrier, an electronic component mounted at the carrier, and an encapsulant encapsulating at least part of the electronic component and at least part of the carrier. Electrically insulating material covers electrically conductive material of the carrier at said first main face. The encapsulant comprises at least one step at the first main face.

Abstract: A package for mounting on a mounting base is disclosed. In one example, the package comprises a carrier, an electronic component mounted at the carrier, leads electrically coupled with the electronic component and to be electrically coupled with the mounting base, and a linear spacer for defining a spacing with respect to the carrier.

Abstract: A semiconductor device module includes a package carrier having an opening, wherein in the opening there is disposed a semiconductor package including a semiconductor die, an encapsulant, and first vertical contacts, wherein the encapsulant at least partially covers the semiconductor die, and the first vertical contacts are connected to the semiconductor die and extend at least partially through the encapsulant, and a first outer metallic contact layer electrically connected to the first vertical contacts.

Abstract: In an embodiment, an assembly includes an electronic component, a fixing member, a resilient member and a substrate having a first surface. The electronic component includes a heat-generating semiconductor device, a die pad and a plastic housing. The heat-generating semiconductor device is mounted on a first surface of the die pad, and the die pad is at least partially embedded in the plastic housing. The resilient member is engaged under compression between an upper side of the electronic component and a lower surface of the fixing member and the fixing member secures the electronic component to the first surface of the substrate.

Abstract: A semiconductor device includes a die carrier, a semiconductor die disposed on a main face of the die carrier, the semiconductor die including one or more contact pads, an encapsulant covering at least partially the semiconductor die and at least a portion of the main face of the die carrier, an insulation layer covering the encapsulant, and one or more electrical interconnects, each being connected with one of the one or more contact pads of the semiconductor die and extending through the encapsulant.