Patents by Inventor Bernd SCHMOELZER

Bernd SCHMOELZER has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 12648456
    Abstract: A semiconductor package is disclosed. In one example, the semiconductor package comprises a package body and a second die pad at least partially encapsulated in the package body. A first semiconductor die is at least partially encapsulated in the package body and arranged on the first die pad. A further device at least partially encapsulated in the package body and arranged on the second die pad. At least one first lead is connected with the first contact pad of the first semiconductor die. At least one second lead is connected with the second contact pad of the further device. An electrical conductor is connected between the at least one first lead and the at least one second lead, the electrical conductor being completely encapsulated in the package body.
    Type: Grant
    Filed: May 9, 2023
    Date of Patent: June 2, 2026
    Assignee: Infineon Technologies AG
    Inventors: Lee Shuang Wang, Marta Alomar Dominguez, Marcus Böhm, Edward Fürgut, Chii Shang Hong, Teck Sim Lee, Bernd Schmoelzer
  • Publication number: 20260107826
    Abstract: A semiconductor package and method are disclosed. In one example, the semiconductor package includes a package body. A first diepad is at least partially uncovered by the package body at the first main surface. A second diepad is at least partially uncovered by the package body at the first main surface. A first semiconductor chip is arranged on the first diepad. A second semiconductor chip is arranged on the second diepad. The semiconductor package further includes at least one lead protruding out of the package body at the side surface. A first groove and a second groove are formed in the first main surface. The method includes a method of making the semiconductor package.
    Type: Application
    Filed: December 16, 2025
    Publication date: April 16, 2026
    Applicant: Infineon Technologies AG
    Inventors: Chii Shang HONG, Li Fong CHONG, Yee Beng DARYL YEOW, Edward FÜRGUT, Mei Fen HIEW, Azlina KASSIM, Ralf OTREMBA, Bernd SCHMOELZER, Joon Shyan TAN, Lee Shuang WANG
  • Patent number: 12512380
    Abstract: A semiconductor package is disclosed. In one example, the semiconductor package includes a package body. A first diepad is at least partially uncovered by the package body at the first main surface. A second diepad is at least partially uncovered by the package body at the first main surface. A first semiconductor chip is arranged on the first diepad. A second semiconductor chip is arranged on the second diepad. The semiconductor package further includes at least one lead protruding out of the package body at the side surface. A first groove is formed in the first main surface, wherein the first groove is arranged between the first diepad and the second diepad, and a second groove is formed in the first main surface, wherein the second groove is arranged between the at least one lead and at least one of the first diepad and the second diepad.
    Type: Grant
    Filed: March 8, 2023
    Date of Patent: December 30, 2025
    Assignee: Infineon Technologies AG
    Inventors: Chii Shang Hong, Li Fong Chong, Yee Beng Daryl Yeow, Edward Fürgut, Mei Fen Hiew, Azlina Kassim, Ralf Otremba, Bernd Schmoelzer, Joon Shyan Tan, Lee Shuang Wang
  • Patent number: 12506051
    Abstract: A semiconductor package comprising a substrate, at least one semiconductor die disposed on the substrate, at least one electrical connector connected with the semiconductor die, an encapsulant covering the substrate, the at least one semiconductor die, and at least partially the electrical connector, the encapsulant comprising a recess formed into a main surface of the encapsulant, wherein the at least one electrical connector is exposed within the recess.
    Type: Grant
    Filed: September 21, 2022
    Date of Patent: December 23, 2025
    Assignee: Infineon Technologies Austria AG
    Inventors: Julian Treu, Ivan Nikitin, Bernd Schmoelzer
  • Patent number: 12463116
    Abstract: A method for fabricating a semiconductor device includes: providing a die carrier; disposing a semiconductor die on a main face of the die carrier, the semiconductor die having one or more contact pads; applying an encapsulant at least partially to the semiconductor die and at least a portion of the main face of the die carrier; applying an insulation layer to the encapsulant; and fabricating electrical interconnects by forming openings into the encapsulant and the insulation layer and filling a conductive material into the openings. Additional methods for fabricating a semiconductor device are described.
    Type: Grant
    Filed: February 29, 2024
    Date of Patent: November 4, 2025
    Assignee: Infineon Technologies Austria AG
    Inventors: Edward Fuergut, Achim Althaus, Martin Gruber, Marco Nicolas Mueller, Bernd Schmoelzer, Wolfgang Scholz, Mark Thomas
  • Patent number: 12438068
    Abstract: A stacked module arrangement includes: a first molded electronic module; a second molded electronic module; and an interface by which the first molded electronic module and the second molded electronic module are physically and electrically connected to one another in a stacked configuration. The first molded electronic module is a power electronic module having a maximum breakdown voltage of at least 40V and a maximum DC current of at least 10 A.
    Type: Grant
    Filed: January 18, 2022
    Date of Patent: October 7, 2025
    Assignee: Infineon Technologies Austria AG
    Inventors: Peter Luniewski, Ivan Nikitin, Bernd Schmoelzer
  • Publication number: 20240395646
    Abstract: A package is disclosed. In one example, the package includes a first main face for mounting a heat sink and an opposing second main face for being mounted on a mounting base. The package comprises a carrier, an electronic component mounted at the carrier, and an encapsulant encapsulating at least part of the electronic component and at least part of the carrier. Electrically insulating material covers electrically conductive material of the carrier at said first main face. The encapsulant comprises at least one step at the first main face.
    Type: Application
    Filed: August 1, 2024
    Publication date: November 28, 2024
    Applicant: Infineon Technologies AG
    Inventors: Edward FUERGUT, Chii Shang HONG, Teck Sim LEE, Bernd SCHMOELZER, Ke Yan TEAN, Lee Shuang WANG
  • Patent number: 12125772
    Abstract: A method includes providing a first lead frame that includes a first die pad and a first row of leads, providing a connection lug, mounting a first semiconductor die on the first die pad, the first semiconductor die including first and second voltage blocking terminals, electrically connecting the connection lug to one of the first and second voltage blocking terminals, electrically connecting a first one of the leads from the first row to an opposite one of the first and second voltage blocking terminals, and forming an encapsulant body of electrically insulating material that encapsulates first die pad and the first semiconductor die. After forming the encapsulant body, the first row of leads each protrude out of a first outer face of the encapsulant body and the connection lug protrudes out of a second outer face of the encapsulant body.
    Type: Grant
    Filed: May 20, 2021
    Date of Patent: October 22, 2024
    Assignee: Infineon Technologies Austria AG
    Inventors: Edward Fuergut, Martin Gruber, Herbert Hopfgartner, Bernd Schmoelzer
  • Patent number: 12094793
    Abstract: A package is disclosed. In one example, the package includes a first main face for mounting a heat sink and an opposing second main face for being mounted on a mounting base. The package comprises a carrier, an electronic component mounted at the carrier, and an encapsulant encapsulating at least part of the electronic component and at least part of the carrier. Electrically insulating material covers electrically conductive material of the carrier at said first main face. The encapsulant comprises at least one step at the first main face.
    Type: Grant
    Filed: October 16, 2023
    Date of Patent: September 17, 2024
    Assignee: Infineon Technologies AG
    Inventors: Edward Fuergut, Chii Shang Hong, Teck Sim Lee, Bernd Schmoelzer, Ke Yan Tean, Lee Shuang Wang
  • Patent number: 12080669
    Abstract: A semiconductor device module includes a package carrier having an opening, wherein in the opening there is disposed a semiconductor package including a semiconductor die, an encapsulant, and first vertical contacts, wherein the encapsulant at least partially covers the semiconductor die, and the first vertical contacts are connected to the semiconductor die and extend at least partially through the encapsulant, and a first outer metallic contact layer electrically connected to the first vertical contacts.
    Type: Grant
    Filed: September 23, 2021
    Date of Patent: September 3, 2024
    Assignee: Infineon Technologies Austria AG
    Inventors: Edward Fuergut, Martin Gruber, Petteri Palm, Bernd Schmoelzer, Wolfgang Scholz, Mark Thomas
  • Publication number: 20240250004
    Abstract: A method for fabricating a semiconductor device includes: providing a die carrier; disposing a semiconductor die on a main face of the die carrier, the semiconductor die having one or more contact pads; applying an encapsulant at least partially to the semiconductor die and at least a portion of the main face of the die carrier; applying an insulation layer to the encapsulant; and fabricating electrical interconnects by forming openings into the encapsulant and the insulation layer and filling a conductive material into the openings. Additional methods for fabricating a semiconductor device are described.
    Type: Application
    Filed: February 29, 2024
    Publication date: July 25, 2024
    Inventors: Edward Fuergut, Achim Althaus, Martin Gruber, Marco Nicolas Mueller, Bernd Schmoelzer, Wolfgang Scholz, Mark Thomas
  • Patent number: 12002739
    Abstract: A semiconductor device includes a die carrier, a semiconductor die disposed on a main face of the die carrier, the semiconductor die including one or more contact pads, an encapsulant covering at least partially the semiconductor die and at least a portion of the main face of the die carrier, an insulation layer covering the encapsulant, and one or more electrical interconnects, each being connected with one of the one or more contact pads of the semiconductor die and extending through the encapsulant.
    Type: Grant
    Filed: February 11, 2021
    Date of Patent: June 4, 2024
    Assignee: Infineon Technologies Austria AG
    Inventors: Edward Fuergut, Achim Althaus, Martin Gruber, Marco Nicolas Mueller, Bernd Schmoelzer, Wolfgang Scholz, Mark Thomas
  • Publication number: 20240170377
    Abstract: A semiconductor package includes: a semiconductor transistor die having an emitter/source contact pad, a drain/collector contact pad, and a gate contact pad; at least two electrical connectors disposed in a symmetrical manner on opposing lateral sides of the semiconductor die and connected with at least one of the contact pads; and an encapsulant embedding the semiconductor transistor die. The two or more electrical connectors extend through the encapsulant and form protruding sections above an upper surface of the encapsulant.
    Type: Application
    Filed: November 9, 2023
    Publication date: May 23, 2024
    Inventors: Bernd Schmoelzer, Wolfgang Scholz, Ivan Nikitin
  • Publication number: 20240162205
    Abstract: A power semiconductor package comprises a leadframe comprising a first die pad, a second die pad and a plurality of external contacts. The first and second die pads are separated by a first gap. A power semiconductor die is arranged on and electrically coupled to a first side of the first die pad. A diode is arranged on and electrically coupled to a first side of the second die pad. A molded body encapsulates the power semiconductor die and the diode, the molded body having a first side, an opposite second side and lateral sides connecting the first and second sides. A second side of the first die pad is exposed from the second side of the molded body. A second side of the second die pad is completely covered by an electrically insulating material.
    Type: Application
    Filed: November 10, 2023
    Publication date: May 16, 2024
    Applicant: Infineon Technologies Austria AG
    Inventors: Marcus BÖHM, Stefan WÖTZEL, Andreas GRASSMANN, Bernd SCHMOELZER, Uwe SCHINDLER
  • Patent number: 11942383
    Abstract: A package for mounting on a mounting base is disclosed. In one example, the package comprises a carrier, an electronic component mounted at the carrier, leads electrically coupled with the electronic component and to be electrically coupled with the mounting base, and a linear spacer for defining a spacing with respect to the carrier.
    Type: Grant
    Filed: October 14, 2021
    Date of Patent: March 26, 2024
    Assignee: Infineon Technologies AG
    Inventors: Edward Fuergut, Chii Shang Hong, Teck Sim Lee, Ralf Otremba, Daniel Pedone, Bernd Schmoelzer
  • Publication number: 20240038612
    Abstract: A package is disclosed. In one example, the package includes a first main face for mounting a heat sink and an opposing second main face for being mounted on a mounting base. The package comprises a carrier, an electronic component mounted at the carrier, and an encapsulant encapsulating at least part of the electronic component and at least part of the carrier. Electrically insulating material covers electrically conductive material of the carrier at said first main face. The encapsulant comprises at least one step at the first main face.
    Type: Application
    Filed: October 16, 2023
    Publication date: February 1, 2024
    Applicant: Infineon Technologies AG
    Inventors: Edward FUERGUT, Chii Shang HONG, Teck Sim LEE, Bernd SCHMOELZER, Ke Yan TEAN, Lee Shuang WANG
  • Patent number: 11876028
    Abstract: A package is disclosed. In one example, the package includes a first main face for mounting a heat sink and an opposing second main face for being mounted on a mounting base. The package comprises a carrier, an electronic component mounted at the carrier, and an encapsulant encapsulating at least part of the electronic component and at least part of the carrier. Electrically insulating material covers electrically conductive material of the carrier at said first main face. The encapsulant comprises at least one step at the first main face.
    Type: Grant
    Filed: October 15, 2021
    Date of Patent: January 16, 2024
    Assignee: Infineon Technologies AG
    Inventors: Edward Fuergut, Chii Shang Hong, Teck Sim Lee, Bernd Schmoelzer, Ke Yan Tean, Lee Shuang Wang
  • Publication number: 20240014104
    Abstract: A semiconductor package comprises a semiconductor transistor circuit comprising a semiconductor transistor die comprising die terminals, including a collector/drain, a source/emitter, a sense source/sense emitter, a gate, and a load path, a driver line connected with the gate, and a gate control loop in which the a sense source/sense emitter is connected with the driver line, a plurality of external contacts comprising at least one first external contact connected with the drain/collector, at least one second external contact connected with the source/emitter, a third external contact connected with the a sense source/sense emitter, and a fourth external contact connected with the gate, wherein the plurality of external contacts are arranged or configured to reduce or utilize the magnetic coupling induced by a load current flowing through the load path.
    Type: Application
    Filed: June 30, 2023
    Publication date: January 11, 2024
    Inventors: Edward Fürgut, Wolfgang Scholz, Christian Baeumler, Thomas Basler, Xing Liu, Bernd Schmoelzer
  • Publication number: 20230378011
    Abstract: An electronic device module includes: a core layer having an opening; an electronic device disposed in the opening, one or both of the core layer and the electronic device being at least partially covered by an adhesion promoter layer; and an encapsulant layer at least partially embedding the core layer and the electronic device.
    Type: Application
    Filed: May 10, 2023
    Publication date: November 23, 2023
    Inventors: Edward Fürgut, Harry Sax, Bernd Schmoelzer
  • Publication number: 20230361009
    Abstract: A semiconductor package is disclosed. In one example, the semiconductor package comprises a package body and a second die pad at least partially encapsulated in the package body. A first semiconductor die is at least partially encapsulated in the package body and arranged on the first die pad. A further device at least partially encapsulated in the package body and arranged on the second die pad. At least one first lead is connected with the first contact pad of the first semiconductor die. At least one second lead is connected with the second contact pad of the further device. An electrical conductor is connected between the at least one first lead and the at least one second lead, the electrical conductor being completely encapsulated in the package body.
    Type: Application
    Filed: May 9, 2023
    Publication date: November 9, 2023
    Applicant: Infineon Technologies AG
    Inventors: Lee Shuang WANG, Marta ALOMAR DOMINGUEZ, Marcus BÖHM, Edward FÜRGUT, Chii Shang HONG, Teck Sim LEE, Bernd SCHMOELZER