Patents by Inventor Bernd SCHMOELZER

Bernd SCHMOELZER has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20220157682
    Abstract: A package is disclosed. In one example, the package includes a first main face for mounting a heat sink and an opposing second main face for being mounted on a mounting base. The package comprises a carrier, an electronic component mounted at the carrier, and an encapsulant encapsulating at least part of the electronic component and at least part of the carrier. Electrically insulating material covers electrically conductive material of the carrier at said first main face. The encapsulant comprises at least one step at the first main face.
    Type: Application
    Filed: October 15, 2021
    Publication date: May 19, 2022
    Applicant: Infineon Technologies AG
    Inventors: Edward FUERGUT, Chii Shang HONG, Teck Sim LEE, Bernd SCHMOELZER, Ke Yan TEAN, Lee Shuang WANG
  • Publication number: 20220148934
    Abstract: A package for mounting on a mounting base is disclosed. In one example, the package comprises a carrier, an electronic component mounted at the carrier, leads electrically coupled with the electronic component and to be electrically coupled with the mounting base, and a linear spacer for defining a spacing with respect to the carrier.
    Type: Application
    Filed: October 14, 2021
    Publication date: May 12, 2022
    Applicant: Infineon Technologies AG
    Inventors: Edward Fuergut, Chii Shang Hong, Teck Sim Lee, Ralf Otremba, Daniel Pedone, Bernd Schmoelzer
  • Publication number: 20220102311
    Abstract: A semiconductor device module includes a package carrier having an opening, wherein in the opening there is disposed a semiconductor package including a semiconductor die, an encapsulant, and first vertical contacts, wherein the encapsulant at least partially covers the semiconductor die, and the first vertical contacts are connected to the semiconductor die and extend at least partially through the encapsulant, and a first outer metallic contact layer electrically connected to the first vertical contacts.
    Type: Application
    Filed: September 23, 2021
    Publication date: March 31, 2022
    Inventors: Edward Fuergut, Martin Gruber, Petteri Palm, Bernd Schmoelzer, Wolfgang Scholz, Mark Thomas
  • Patent number: 11211304
    Abstract: In an embodiment, an assembly includes an electronic component, a fixing member, a resilient member and a substrate having a first surface. The electronic component includes a heat-generating semiconductor device, a die pad and a plastic housing. The heat-generating semiconductor device is mounted on a first surface of the die pad, and the die pad is at least partially embedded in the plastic housing. The resilient member is engaged under compression between an upper side of the electronic component and a lower surface of the fixing member and the fixing member secures the electronic component to the first surface of the substrate.
    Type: Grant
    Filed: August 17, 2018
    Date of Patent: December 28, 2021
    Assignee: Infineon Technologies Austria AG
    Inventors: Ralf Otremba, Guenther Lohmann, Bernd Schmoelzer, Fabian Schnoy
  • Publication number: 20210249334
    Abstract: A semiconductor device includes a die carrier, a semiconductor die disposed on a main face of the die carrier, the semiconductor die including one or more contact pads, an encapsulant covering at least partially the semiconductor die and at least a portion of the main face of the die carrier, an insulation layer covering the encapsulant, and one or more electrical interconnects, each being connected with one of the one or more contact pads of the semiconductor die and extending through the encapsulant.
    Type: Application
    Filed: February 11, 2021
    Publication date: August 12, 2021
    Inventors: Edward Fuergut, Achim Althaus, Martin Gruber, Marco Nicolas Mueller, Bernd Schmoelzer, Wolfgang Scholz, Mark Thomas
  • Patent number: 10755999
    Abstract: A power semiconductor arrangement includes a carrier and packages. Each package: encloses a power semiconductor die having first and second load terminals and configured to conduct a die load current between the load terminals; has a package body with a top side, a footprint side and sidewalls extending from the footprint side to the top side; a lead frame structure configured to electrically and mechanically couple the package to the carrier with the package footprint side facing the carrier, the lead frame structure including at least one first outside terminal electrically connected with the first load terminal of the die; a top layer arranged at the package top side and electrically connected with the second load terminal of the die. A top heatsink is attached to each package top layer, electrically contacted to each package top layer, and configured to conduct at least a sum of the die load currents.
    Type: Grant
    Filed: March 25, 2019
    Date of Patent: August 25, 2020
    Assignee: Infineon Technologies Austria AG
    Inventors: Ralf Otremba, Uwe Kirchner, Matteo-Alessandro Kutschak, Klaus Schiess, Bernd Schmoelzer
  • Patent number: 10699978
    Abstract: A package encloses a power semiconductor die and has a package body with a package top side, package footprint side and package sidewalls. The die has first and second load terminals for blocking a blocking voltage. A lead frame structure electrically and mechanically couples the package to a support and includes an outside terminal extending out of the package footprint side and/or the sidewalls, and is electrically connected with the first load terminal. A top layer arranged at the package top side is electrically connected with the second load terminal. A creepage length between the electrical potential of the outside terminal and the electrical potential of the top layer is defined by a package body surface contour. The surface contour is formed at least by the package top side and package sidewall. At least one structural feature also forms the surface contour is configured to increase the creepage length.
    Type: Grant
    Filed: September 7, 2018
    Date of Patent: June 30, 2020
    Assignee: Infineon Technologies Austria AG
    Inventors: Ralf Otremba, Amirul Afiq Hud, Teck Sim Lee, Xaver Schloegel, Bernd Schmoelzer
  • Publication number: 20190295920
    Abstract: A power semiconductor arrangement includes a carrier and packages. Each package: encloses a power semiconductor die having first and second load terminals and configured to conduct a die load current between the load terminals; has a package body with a top side, a footprint side and sidewalls extending from the footprint side to the top side; a lead frame structure configured to electrically and mechanically couple the package to the carrier with the package footprint side facing the carrier, the lead frame structure including at least one first outside terminal electrically connected with the first load terminal of the die; a top layer arranged at the package top side and electrically connected with the second load terminal of the die. A top heatsink is attached to each package top layer, electrically contacted to each package top layer, and configured to conduct at least a sum of the die load currents.
    Type: Application
    Filed: March 25, 2019
    Publication date: September 26, 2019
    Inventors: Ralf Otremba, Uwe Kirchner, Matteo-Alessandro Kutschak, Klaus Schiess, Bernd Schmoelzer
  • Patent number: 10373897
    Abstract: A device may include a carrier, a semiconductor chip arranged over a first surface of the carrier, and an encapsulation body comprising six side surfaces and encapsulating the semiconductor chip. A second surface of the carrier opposite to the first surface of the carrier is exposed from the encapsulation body. The device may further include electrical contact elements electrically coupled to the semiconductor chip and protruding out of the encapsulation body exclusively through two opposing side surfaces of the encapsulation body which have the smallest surface areas of all the side surfaces of the encapsulation body, and an electrically insulating layer arranged over the exposed second surface of the carrier.
    Type: Grant
    Filed: December 13, 2016
    Date of Patent: August 6, 2019
    Assignee: INFINEON TECHNOLOGIES AUSTRIA AG
    Inventors: Ralf Otremba, Felix Grawert, Amirul Afiq Hud, Uwe Kirchner, Teck Sim Lee, Guenther Lohmann, Hwee Yin Low, Edward Fuergut, Bernd Schmoelzer, Fabian Schnoy, Franz Stueckler
  • Publication number: 20190080973
    Abstract: A package encloses a power semiconductor die and has a package body with a package top side, package footprint side and package sidewalls. The die has first and second load terminals for blocking a blocking voltage. A lead frame structure electrically and mechanically couples the package to a support and includes an outside terminal extending out of the package footprint side and/or the sidewalls, and is electrically connected with the first load terminal. A top layer arranged at the package top side is electrically connected with the second load terminal. A creepage length between the electrical potential of the outside terminal and the electrical potential of the top layer is defined by a package body surface contour. The surface contour is formed at least by the package top side and package sidewall. At least one structural feature also forms the surface contour is configured to increase the creepage length.
    Type: Application
    Filed: September 7, 2018
    Publication date: March 14, 2019
    Inventors: Ralf Otremba, Amirul Afiq Hud, Teck Sim Lee, Xaver Schloegel, Bernd Schmoelzer
  • Publication number: 20190057923
    Abstract: In an embodiment, an assembly includes an electronic component, a fixing member, a resilient member and a substrate having a first surface. The electronic component includes a heat-generating semiconductor device, a die pad and a plastic housing. The heat-generating semiconductor device is mounted on a first surface of the die pad, and the die pad is at least partially embedded in the plastic housing. The resilient member is engaged under compression between an upper side of the electronic component and a lower surface of the fixing member and the fixing member secures the electronic component to the first surface of the substrate.
    Type: Application
    Filed: August 17, 2018
    Publication date: February 21, 2019
    Inventors: Ralf Otremba, Guenther Lohmann, Bernd Schmoelzer, Fabian Schnoy
  • Patent number: 9972576
    Abstract: The semiconductor chip package comprises a semiconductor chip, and an encapsulation body encapsulating the semiconductor chip, wherein the encapsulation body comprises a semiconductor chip; an encapsulation body encapsulating the semiconductor chip, wherein the encapsulation body comprises two opposing main faces and side faces which connect the two main faces with each other, wherein the side face have a smaller surface area than the main faces, respectively, and wherein a marking is provided on at least one of the side faces.
    Type: Grant
    Filed: November 24, 2016
    Date of Patent: May 15, 2018
    Assignee: Infineon Technologies Austria AG
    Inventors: Ralf Otremba, Teck Sim Lee, Amirul Afiq Hud, Fabian Schnoy, Felix Grawert, Uwe Kirchner, Bernd Schmoelzer, Franz Stueckler
  • Publication number: 20170179009
    Abstract: A device may include a carrier, a semiconductor chip arranged over a first surface of the carrier, and an encapsulation body comprising six side surfaces and encapsulating the semiconductor chip. A second surface of the carrier opposite to the first surface of the carrier is exposed from the encapsulation body. The device may further include electrical contact elements electrically coupled to the semiconductor chip and protruding out of the encapsulation body exclusively through two opposing side surfaces of the encapsulation body which have the smallest surface areas of all the side surfaces of the encapsulation body, and an electrically insulating layer arranged over the exposed second surface of the carrier.
    Type: Application
    Filed: December 13, 2016
    Publication date: June 22, 2017
    Inventors: Ralf Otremba, Felix Grawert, Amirul Afiq Hud, Uwe Kirchner, Teck Sim Lee, Guenther Lohmann, Hwee Yin Low, Edward Fuergut, Bernd Schmoelzer, Fabian Schnoy, Franz Stueckler
  • Publication number: 20170148743
    Abstract: The semiconductor chip package comprises a semiconductor chip, and an encapsulation body encapsulating the semiconductor chip, wherein the encapsulation body comprises a semiconductor chip; an encapsulation body encapsulating the semiconductor chip, wherein the encapsulation body comprises two opposing main faces and side faces which connect the two main faces with each other, wherein the side face have a smaller surface area than the main faces, respectively, and wherein a marking is provided on at least one of the side faces.
    Type: Application
    Filed: November 24, 2016
    Publication date: May 25, 2017
    Inventors: Ralf OTREMBA, Teck Sim LEE, Amirul Afiq HUD, Fabian SCHNOY, Felix GRAWERT, Uwe KIRCHNER, Bernd SCHMOELZER, Franz STUECKLER