Patents by Inventor Bernd ULMANN

Bernd ULMANN has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 12625834
    Abstract: There is provided an analog circuit comprising: a plurality of analog functions, which are divided into at least two groups of analog functions, and an interconnection structure configured to interconnect the plurality of analog functions so as to enable transfer of both voltage and current signals between analog functions among the plurality of analog functions. The interconnection structure comprises at least two hierarchy levels of interconnections, wherein a local-bus hierarchy level is configured to interconnect analog functions of a respective group, and a global-bus hierarchy level is configured to interconnect analog functions of the plurality of groups. The local-bus hierarchy level comprises voltage signal lines for transferring voltage signals and/or current signal lines for transferring current signals, and the global-bus hierarchy level comprises voltage signal lines for transferring voltage signals and/or current signal lines for transferring current signals.
    Type: Grant
    Filed: June 11, 2021
    Date of Patent: May 12, 2026
    Assignee: ANABRID GMBH
    Inventors: Lars Heimann, Bernd Ulmann, Sven Köppel
  • Patent number: 12299509
    Abstract: There is provided a linearized multiplier configured to produce an output current representing a product of a first input voltage and a second input voltage, comprising: a first transconductance stage which is configured to input the first input voltage and to output a first pair of differential currents, wherein the first transconductance stage comprises a negative feedback network, at least one second transconductance stage which is configured to input the second input voltage and to output a pre-distorted voltage of the second input voltage, wherein each second transconductance stage comprises a negative feedback network, a pair of third transconductance stages, each of which is configured to input a voltage corresponding to the pre-distorted voltage of the second input voltage and to output a second pair of differential currents, when being supplied with a bias current corresponding to a respective current of the first pair of differential currents.
    Type: Grant
    Filed: December 14, 2021
    Date of Patent: May 13, 2025
    Assignee: ANABRID GMBH
    Inventors: Lars Heimann, Bernd Ulmann, Sven Koeppel
  • Publication number: 20240289293
    Abstract: There is provided an analog circuit comprising: a plurality of analog functions, which are divided into at least two groups of analog functions, and an interconnection structure configured to interconnect the plurality of analog functions so as to enable transfer of both voltage and current signals between analog functions among the plurality of analog functions. The interconnection structure comprises at least two hierarchy levels of interconnections, wherein a local-bus hierarchy level is configured to interconnect analog functions of a respective group, and a global-bus hierarchy level is configured to interconnect analog functions of the plurality of groups. The local-bus hierarchy level comprises voltage signal lines for transferring voltage signals and/or current signal lines for transferring current signals, and the global-bus hierarchy level comprises voltage signal lines for transferring voltage signals and/or current signal lines for transferring current signals.
    Type: Application
    Filed: June 11, 2021
    Publication date: August 29, 2024
    Inventors: Lars HEIMANN, Bernd ULMANN, Sven KÖPPEL
  • Publication number: 20240070406
    Abstract: There is provided a linearized multiplier configured to produce an output current representing a product of a first input voltage and a second input voltage, comprising: a first transconductance stage which is configured to input the first input voltage and to output a first pair of differential currents, wherein the first transconductance stage comprises a negative feedback network, at least one second transconductance stage which is configured to input the second input voltage and to output a pre-distorted voltage of the second input voltage, wherein each second transconductance stage comprises a negative feedback network, a pair of third transconductance stages, each of which is configured to input a voltage corresponding to the pre-distorted voltage of the second input voltage and to output a second pair of differential currents, when being supplied with a bias current corresponding to a respective current of the first pair of differential currents.
    Type: Application
    Filed: December 14, 2021
    Publication date: February 29, 2024
    Inventors: Lars HEIMANN, Bernd ULMANN, Seven KÖPPEL