Patents by Inventor Bernd Waidhas

Bernd Waidhas has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 11404339
    Abstract: A semiconductor device and method of including peripheral devices into a package is disclosed. In one example, a peripheral device includes a passive device such as a capacitor or an inductor. Examples are shown that include a peripheral device that is substantially the same thickness as a die or a die assembly. Examples are further shown that use this configuration in a fan out process to form semiconductor devices.
    Type: Grant
    Filed: June 5, 2020
    Date of Patent: August 2, 2022
    Assignee: Intel Corporation
    Inventors: Lizabeth Keser, Bernd Waidhas, Thomas Ort, Thomas Wagner
  • Publication number: 20220238440
    Abstract: A system-in-package apparatus includes a semiconductive bridge that uses bare-die pillars to couple with a semiconductive device such as a processor die. The apparatus achieves a thin form factor.
    Type: Application
    Filed: April 8, 2022
    Publication date: July 28, 2022
    Inventors: Georg SEIDEMANN, Thomas WAGNER, Adreas WOLTER, Bernd WAIDHAS
  • Patent number: 11380616
    Abstract: Fan Out Package-On-Package (PoP) assemblies in which a second chip is adhered to a non-active side of a first chip. An active side of the first chip embedded in a first package material may be electrically coupled through one or more redistribution layers that fan out to package interconnects on a first side of the POP. A second chip may be adhered, with a second package material, to the non-active side of the first chip. An active side of the second chip may be electrically coupled to the package interconnects through a via structure extending through the first package material. Second interconnects between the second chip, or a package thereof, may contact the via structure. Use of the second package material as an adhesive may improve positional stability of the second chip to facilitate wafer-level assembly techniques.
    Type: Grant
    Filed: May 16, 2018
    Date of Patent: July 5, 2022
    Assignee: Intel IP Corporation
    Inventors: David O'Sullivan, Bernd Waidhas, Thomas Huber
  • Patent number: 11374323
    Abstract: A patch antenna array is fabricated with a package-on-package setup that contains a transceiver. The patch antenna array has a footprint that intersects the transceiver footprint. The package-on-package setup includes through-mold vias that couple to a redistribution layer disposed between the patch antennas and the package-on-package setup.
    Type: Grant
    Filed: March 31, 2017
    Date of Patent: June 28, 2022
    Assignee: Intel Corporation
    Inventors: Andreas Augustin, Sonja Koller, Bernd Waidhas, Georg Seidemann, Andreas Wolter, Stephan Stoeckl, Thomas Wagner, Josef Hagn
  • Publication number: 20220199562
    Abstract: Embodiments disclosed herein include electronic package and methods of forming such packages. In an embodiment, an electronic package comprises a mold layer and a first die embedded in the mold layer. In an embodiment, the first die comprises first pads at a first pitch and second pads at a second pitch. In an embodiment, the electronic package further comprises a second die embedded in the mold layer, where the second die comprises third pads at the first pitch and fourth pads at the second pitch. In an embodiment, a bridge die is embedded in the mold layer, and the bridge die electrically couples the second pads to the fourth pads.
    Type: Application
    Filed: December 22, 2020
    Publication date: June 23, 2022
    Inventors: Bernd WAIDHAS, Andreas WOLTER, Georg SEIDEMANN, Thomas WAGNER
  • Publication number: 20220115323
    Abstract: A system-in-package apparatus includes a semiconductive bridge that uses bare-die pillars to couple with a semiconductive device such as a processor die. The apparatus achieves a thin form factor.
    Type: Application
    Filed: December 17, 2021
    Publication date: April 14, 2022
    Inventors: Georg SEIDEMANN, Thomas WAGNER, Adreas WOLTER, Bernd WAIDHAS
  • Patent number: 11270941
    Abstract: A system-in-package apparatus includes a semiconductive bridge that uses bare-die pillars to couple with a semiconductive device such as a processor die. The apparatus achieves a thin form factor.
    Type: Grant
    Filed: December 29, 2016
    Date of Patent: March 8, 2022
    Assignee: Intel Corporation
    Inventors: Georg Seidemann, Thomas Wagner, Andreas Wolter, Bernd Waidhas
  • Publication number: 20220051990
    Abstract: A face-up fan-out electronic package including at least one passive component located on a support. The electronic package can include a die. The die can include a plurality of conductive pillars having a proximal end communicatively coupled to the first side of the die and a distal end opposite the proximal end. A mold can at least partially surround the die. The mold can include a first surface that is coplanar with the distal end of the conductive pillars and a second surface opposing the first surface. In an example, the passive component can include a body and a lead. The passive component can be located within the mold. The lead can be coplanar with the first surface, and the body can be located at a distance from the second surface. The support can be located between the body and the second surface.
    Type: Application
    Filed: November 1, 2021
    Publication date: February 17, 2022
    Inventors: Lizabeth Keser, Thomas Ort, Thomas Wagner, Bernd Waidhas
  • Publication number: 20220015244
    Abstract: A printed wiring-board island relieves added complexity to a printed circuit board. The printed wiring-board island creates an island form factor in the printed circuit board. Coupling of a semiconductive device package to the printed wiring-board island includes a ball-grid array. The ball-grid array can at least partially penetrate the printed wiring-board island.
    Type: Application
    Filed: September 27, 2021
    Publication date: January 13, 2022
    Inventors: Georg Seidemann, Sonja Koller, Bernd Waidhas
  • Patent number: 11211337
    Abstract: A face-up fan-out electronic package including at least one passive component located on a support. The electronic package can include a die. The die can include a plurality of conductive pillars having a proximal end communicatively coupled to the first side of the die and a distal end opposite the proximal end. A mold can at least partially surround the die. The mold can include a first surface that is coplanar with the distal end of the conductive pillars and a second surface opposing the first surface. In an example, the passive component can include a body and a lead. The passive component can be located within the mold. The lead can be coplanar with the first surface, and the body can be located at a distance from the second surface. The support can be located between the body and the second surface.
    Type: Grant
    Filed: December 4, 2019
    Date of Patent: December 28, 2021
    Assignee: Intel Corporation
    Inventors: Lizabeth Keser, Thomas Ort, Thomas Wagner, Bernd Waidhas
  • Patent number: 11177220
    Abstract: Electronics devices, having vertical and lateral redistribution interconnects, are disclosed. An electronics device comprises an electronics component (e.g., die, substrate, integrated device, etc.), a die(s), and a separately formed redistribution connection layer electrically coupling the die(s) to the electronics component. The redistribution connection layer comprises dielectric layers on either side of at least one redistribution layer. The dielectric layers comprise openings that expose contact pads of the at least one redistribution layer for electrically coupling die(s) and components to each other via the redistribution connection layer. The redistribution connection layer is flexible and wrap/folded around side edges of die(s) to minimize vertical vias. Various devices and associated processes are provided.
    Type: Grant
    Filed: April 1, 2017
    Date of Patent: November 16, 2021
    Assignee: Intel Corporation
    Inventors: Georg Seidemann, Andreas Wolter, Bernd Waidhas, Thomas Wagner
  • Patent number: 11145577
    Abstract: A system-in-package apparatus includes a square wave lead frame that provides a recess for a first semiconductive device as well as a feature for a second device. The system-in-package apparatus includes a printed wiling board that is wrapped onto the lead frame after a manner to enclose the first semiconductive device into the recess.
    Type: Grant
    Filed: December 29, 2016
    Date of Patent: October 12, 2021
    Assignee: Intel Corporation
    Inventors: Sonja Koller, Georg Seidemann, Reinhard Mahnkopf, Bernd Waidhas
  • Patent number: 11134573
    Abstract: A printed wiring-board island relieves added complexity to a printed circuit board. The printed wiring-board island creates an island form factor in the printed circuit board. Coupling of a semiconductive device package to the printed wiring-board island includes a ball-grid array. The ball-grid array can at least partially penetrate the printed wiring-board island.
    Type: Grant
    Filed: September 29, 2017
    Date of Patent: September 28, 2021
    Assignee: Intel Corporation
    Inventors: Georg Seidemann, Sonja Koller, Bernd Waidhas
  • Patent number: 11127813
    Abstract: The present disclosure is directed to systems and methods for fabricating a semiconductor inductor that includes a coil deposited on a stop layer that is deposited on a sacrificial substrate. The semiconductor inductor may be fabricated on a silicon wafer and singulated. The sacrificial substrate beneficially provides structural support for the singulated semiconductor inductor. The singulated semiconductor inductor advantageously requires minimal active die surface area. The removal of the sacrificial substrate after coupling to the active die beneficially reduces the overall thickness (or height) of the semiconductor package, providing a decided advantage in low profile, portable, electronic devices.
    Type: Grant
    Filed: June 30, 2017
    Date of Patent: September 21, 2021
    Assignee: Intel Corporation
    Inventors: Georg Seidemann, Bernd Waidhas, Thomas Wagner, Andreas Wolter, Andreas Augustin
  • Publication number: 20210273342
    Abstract: Some embodiments include packages and methods of making the packages. One of the packages includes a ground layer (e.g., a ground plane) of metal formed over a chip of die, an antenna element of metal formed over the ground layer, and a dielectric lens formed over the antenna element. The dielectric lens includes a plurality of dielectric layers that have graded dielectric constants in a decreasing order along a direction from the antenna element toward a top surface of the package.
    Type: Application
    Filed: May 18, 2021
    Publication date: September 2, 2021
    Inventors: Saravana Maruthamuthu, Bernd Waidhas, Andreas Augustin, Georg Seidemann
  • Publication number: 20210193594
    Abstract: Embodiments disclosed herein include semiconductor packages. In a particular embodiment, the semiconductor package is a wafer level chip scale package (WLCSP). In an embodiment, the WLCSP comprises a die. In an embodiment, the die comprises an active surface and a backside surface. The die has a first coefficient of thermal expansion (CTE). In an embodiment, the WLCSP further comprises a channel into the die. In an embodiment, the channel is filled with a stress relief material, where the stress relief material has a second CTE that is greater than the first CTE.
    Type: Application
    Filed: December 19, 2019
    Publication date: June 24, 2021
    Inventors: Stephan STOECKL, Wolfgang MOLZER, Georg SEIDEMANN, Bernd WAIDHAS
  • Patent number: 11031699
    Abstract: Some embodiments include packages and methods of making the packages. One of the packages includes a ground layer (e.g., a ground plane) of metal formed over a chip of die, an antenna element of metal formed over the ground layer, and a dielectric lens formed over the antenna element. The dielectric lens includes a plurality of dielectric layers that have graded dielectric constants in a decreasing order along a direction from the antenna element toward a top surface of the package.
    Type: Grant
    Filed: February 9, 2018
    Date of Patent: June 8, 2021
    Assignee: Intel IP Corporation
    Inventors: Saravana Maruthamuthu, Bernd Waidhas, Andreas Augustin, Georg Seidemann
  • Patent number: 11018114
    Abstract: A semiconductive device stack, includes a baseband processor die with an active surface and a backside surface, and a recess in the backside surface. A recess-seated device is disposed in the recess, and a through-silicon via in the baseband processor die couples the baseband processor die at the active surface to the recess-seated die at the recess. A processor die is disposed on the baseband processor die backside surface, and a memory die is disposed on the processor die. The several dice are coupled by through-silicon via groups.
    Type: Grant
    Filed: July 18, 2019
    Date of Patent: May 25, 2021
    Assignee: Intel IP Corporation
    Inventors: Bernd Waidhas, Georg Seidemann, Andreas Augustin, Laurent Millou, Andreas Wolter, Reinhard Mahnkopf, Stephan Stoeckl, Thomas Wagner
  • Patent number: 10867934
    Abstract: A microelectronic device may include a substrate, a component, a first plate, a second plate, and a shield. The component may be disposed at least partially within the substrate. The first plate may be disposed on a first side of the component. The second plate may be disposed on a second side of the component. The shield may be disposed around at least a portion of a periphery of the component.
    Type: Grant
    Filed: March 27, 2018
    Date of Patent: December 15, 2020
    Assignee: Intel IP Corporation
    Inventors: Saravana Maruthamuthu, Thomas Ort, Andreas Wolter, Andreas Augustin, Veronica Sciriha, Bernd Waidhas
  • Publication number: 20200352035
    Abstract: A printed wiring-board island relieves added complexity to a printed circuit board. The printed wiring-board island creates an island form factor in the printed circuit board. Coupling of a semiconductive device package to the printed wiring-board island includes a ball-rid array. The ball-grid array can at least partially penetrate the printed wiring-board island.
    Type: Application
    Filed: September 29, 2017
    Publication date: November 5, 2020
    Inventors: Georg Seidemann, Sonja Koller, Bernd Waidhas