Patents by Inventor Bernd Waidhas

Bernd Waidhas has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20200352035
    Abstract: A printed wiring-board island relieves added complexity to a printed circuit board. The printed wiring-board island creates an island form factor in the printed circuit board. Coupling of a semiconductive device package to the printed wiring-board island includes a ball-rid array. The ball-grid array can at least partially penetrate the printed wiring-board island.
    Type: Application
    Filed: September 29, 2017
    Publication date: November 5, 2020
    Inventors: Georg Seidemann, Sonja Koller, Bernd Waidhas
  • Publication number: 20200328182
    Abstract: An embedded-bridge substrate connector apparatus includes a patterned reference layer to which a first module and a subsequent module are aligned and the two modules are mated at the patterned reference layer. At least one module includes a silicon bridge connector that bridges to two devices, through the patterned reference layer, to the mated module.
    Type: Application
    Filed: June 29, 2020
    Publication date: October 15, 2020
    Inventors: Bernd WAIDHAS, Georg SEIDEMANN, Andreas WOLTER, Thomas WAGNER, Stephan Stoeckl, Laurent MILLOU
  • Publication number: 20200312781
    Abstract: Embodiments disclosed herein include electronic packages with conformal shields and methods of forming such packages. In an embodiment, the electronic package comprises a die having a first surface, a second surface opposite the first surface, and sidewall surfaces. A redistribution layer is over the first surface of the die, and the redistribution layer comprises a first conductive layer. In an embodiment, an under ball metallization (UBM) layer is over the redistribution layer, and a conductive shield is over the sidewall surfaces of the die and the second surface of the die. In an embodiment, the conductive shield is electrically coupled to the UBM layer.
    Type: Application
    Filed: March 28, 2019
    Publication date: October 1, 2020
    Inventors: Gianni SIGNORINI, Georg SEIDEMANN, Bernd WAIDHAS
  • Publication number: 20200303274
    Abstract: A semiconductor device and method of including peripheral devices into a package is disclosed. In one example, a peripheral device includes a passive device such as a capacitor or an inductor. Examples are shown that include a peripheral device that is substantially the same thickness as a die or a die assembly. Examples are further shown that use this configuration in a fan out process to form semiconductor devices.
    Type: Application
    Filed: June 5, 2020
    Publication date: September 24, 2020
    Inventors: Lizabeth Keser, Bernd Waidhas, Thomas Ort, Thomas Wagner
  • Publication number: 20200251396
    Abstract: A semiconductor device and method is disclosed. Devices shown include a die coupled to an integrated routing layer, wherein the integrated routing layer includes a first width that is wider than the die. Devices shown further included a molded routing layer coupled to the integrated routing layer.
    Type: Application
    Filed: April 22, 2020
    Publication date: August 6, 2020
    Inventors: Lizabeth Keser, Thomas Ort, Thomas Wagner, Bernd Waidhas
  • Patent number: 10727197
    Abstract: An embedded-bridge substrate connector apparatus includes a patterned reference layer to which a first module and a subsequent module are aligned and the two modules are mated at the patterned reference layer. At least one module includes a silicon bridge connector that bridges to two devices, through the patterned reference layer, to the mated module.
    Type: Grant
    Filed: March 21, 2017
    Date of Patent: July 28, 2020
    Assignee: Intel IP Corporation
    Inventors: Bernd Waidhas, Georg Seidemann, Andreas Wolter, Thomas Wagner, Stephan Stoeckl, Laurent Millou
  • Patent number: 10720393
    Abstract: An electronic device may include a semiconductor die. The electronic device may include a first routing layer. The first routing layer may be coupled to the semiconductor die. A first plurality of routing traces may be in electrical communication with the semiconductor die. The first plurality of routing traces may be positioned within a first routing footprint. The first routing footprint may have a width greater than a width of the semiconductor die. A second routing layer may be coupled to the first routing layer. A second plurality of routing traces may be in electrical communication with the first plurality of routing traces. The second plurality of routing traces may be positioned within a second routing footprint. The second routing footprint may have a width greater than the width of the first routing footprint.
    Type: Grant
    Filed: July 1, 2019
    Date of Patent: July 21, 2020
    Assignee: Intel IP Corporation
    Inventors: Lizabeth Keser, Thomas Ort, Thomas Wagner, Bernd Waidhas
  • Publication number: 20200227388
    Abstract: A semiconductor package includes a first semiconductor die, a semiconductor device comprising a second semiconductor die, and one or more wire bond structures. The wire bond structure includes a bond interface portion. The wire bond structure is arranged next to the first semiconductor die. The first semiconductor die and the bond interface portion of the wire bond structure are arranged at the same side of the semiconductor device. An interface contact structure of the semiconductor device is electrically connected to the wire bond structure.
    Type: Application
    Filed: September 29, 2017
    Publication date: July 16, 2020
    Inventors: Bernd Waidhas, Georg Seidemann, Thomas Wagner, Andreas Wolter, Andreas Augustin, Sonja Koller, Thomas Ort, Reinhard Mahnkopf
  • Patent number: 10699980
    Abstract: A semiconductor device and method of including peripheral devices into a package is disclosed. In one example, a peripheral device includes a passive device such as a capacitor or an inductor. Examples are shown that include a peripheral device that is substantially the same thickness as a die or a die assembly. Examples are further shown that use this configuration in a fan out process to form semiconductor devices.
    Type: Grant
    Filed: March 28, 2018
    Date of Patent: June 30, 2020
    Assignee: Intel IP Corporation
    Inventors: Lizabeth Keser, Bernd Waidhas, Thomas Ort, Thomas Wagner
  • Publication number: 20200185490
    Abstract: The present disclosure is directed to systems and methods for fabricating a semiconductor inductor that includes a coil deposited on a stop layer that is deposited on a sacrificial substrate. The semiconductor inductor may be fabricated on a silicon wafer and singulated. The sacrificial substrate beneficially provides structural support for the singulated semiconductor inductor. The singulated semiconductor inductor advantageously requires minimal active die surface area. The removal of the sacrificial substrate after coupling to the active die beneficially reduces the overall thickness (or height) of the semiconductor package, providing a decided advantage in low profile, portable, electronic devices.
    Type: Application
    Filed: June 30, 2017
    Publication date: June 11, 2020
    Applicant: INTEL IP CORPORATION
    Inventors: Georg Seidemann, Bernd WAIDHAS, Thomas WAGNER, Andreas WOLTER, Andreas AUGUSTIN
  • Patent number: 10665522
    Abstract: A semiconductor device and method is disclosed. Devices shown include a die coupled to an integrated routing layer, wherein the integrated routing layer includes a first width that is wider than the die. Devices shown further included a molded routing layer coupled to the integrated routing layer.
    Type: Grant
    Filed: December 22, 2017
    Date of Patent: May 26, 2020
    Assignee: Intel IP Corporation
    Inventors: Lizabeth Keser, Thomas Ort, Thomas Wagner, Bernd Waidhas
  • Patent number: 10658201
    Abstract: A method for forming a carrier substrate for a semiconductor device, the method includes providing a substrate layer including conductive particles embedded in an electrically insulating material and localized heating of the substrate layer along a desired trace by a laser to form a conductive trace of merged particles along the desired trace.
    Type: Grant
    Filed: March 26, 2018
    Date of Patent: May 19, 2020
    Assignee: Intel IP Corporation
    Inventors: Sonja Koller, Georg Seidemann, Bernd Waidhas
  • Publication number: 20200144723
    Abstract: A patch antenna array is fabricated with a package-on-package setup that contains a transceiver. The patch antenna array has a footprint that intersects the transceiver footprint. The package-on-package setup includes through-mold vias that couple to a redistribution layer disposed between the patch antennas and the package-on-package setup.
    Type: Application
    Filed: March 31, 2017
    Publication date: May 7, 2020
    Inventors: Andreas Augustin, Sonja Koller, Bernd Waidhas, Georg Seidemann, Andreas Wolter, Stephan Stoeckl, Thomas Wagner, Josef Hagn
  • Publication number: 20200126922
    Abstract: Electronics devices, having vertical and lateral redistribution interconnects, are disclosed. An electronics device comprises an electronics component (e.g., die, substrate, integrated device, etc.), a die(s), and a separately formed redistribution connection layer electrically coupling the die(s) to the electronics component. The redistribution connection layer comprises dielectric layers on either side of at least one redistribution layer. The dielectric layers comprise openings that expose contact pads of the at least one redistribution layer for electrically coupling die(s) and components to each other via the redistribution connection layer. The redistribution connection layer is flexible and wrap/folded around side edges of die(s) to minimize vertical vias. Various devices and associated processes are provided.
    Type: Application
    Filed: April 1, 2017
    Publication date: April 23, 2020
    Applicant: Intel IP Corporation
    Inventors: Georg Seidemann, Andreas Wolter, Bernd Waidhas, Thomas Wagner
  • Patent number: 10629731
    Abstract: A power mesh-on-die apparatus includes a solder trace that enhances current flow for a power source trace between adjacent power bumps. The solder trace is also applied between power drain bumps on a power drain trace.
    Type: Grant
    Filed: March 11, 2019
    Date of Patent: April 21, 2020
    Assignee: Intel IP Corporation
    Inventors: Bernd Waidhas, Sonja Koller, Georg Seidemann
  • Publication number: 20200111607
    Abstract: A recess in a die backside surface occupies a footprint that accommodates an inductor coil that is formed in metallization above an active surface of the die. Less semiconductive material is therefore close to the inductor coil. A ferromagnetic material is formed in the recess, or a ferromagnetic material is formed on a dielectric layer above the inductor coil. The recess may extend across a die that allows the die to be deflected at the recess.
    Type: Application
    Filed: March 30, 2017
    Publication date: April 9, 2020
    Inventors: Andreas Augustin, Bernd Waidhas, Sonja Koller, Reinhard Mahnkopf, Georg Seidemann
  • Publication number: 20200105678
    Abstract: A face-up fan-out electronic package including at least one passive component located on a support. The electronic package can include a die. The die can include a plurality of conductive pillars having a proximal end communicatively coupled to the first side of the die and a distal end opposite the proximal end. A mold can at least partially surround the die. The mold can include a first surface that is coplanar with the distal end of the conductive pillars and a second surface opposing the first surface. In an example, the passive component can include a body and a lead. The passive component can be located within the mold. The lead can be coplanar with the first surface, and the body can be located at a distance from the second surface. The support can be located between the body and the second surface.
    Type: Application
    Filed: December 4, 2019
    Publication date: April 2, 2020
    Inventors: Lizabeth Keser, Thomas Ort, Thomas Wagner, Bernd Waidhas
  • Publication number: 20200098698
    Abstract: Embodiments include semiconductor packages, such as wafer level chip scale packages (WLCSPs), flip chip chip scale packages (FCCSPs), and fan out packages. The WLCSP includes a first doped region on a second doped region, a dielectric on a redistribution layer, where the dielectric is between the redistribution layer and doped regions. The WLCSP also includes a shield over the doped regions, the dielectric, and the redistribution layer, where the shield includes a plurality of surfaces, and at least one of the plurality of surfaces of the shield is on a top surface of the first doped region. The WLCSP may have interconnects coupled to the second doped region and redistribution layer. The shield may be a conductive shield that is coupled to ground, and the shield may be directly coupled to the redistribution layer and first doped region. The first and second doped regions may include highly doped n-type materials.
    Type: Application
    Filed: September 26, 2018
    Publication date: March 26, 2020
    Inventors: Richard PATTEN, David O'SULLIVAN, Georg SEIDEMANN, Bernd WAIDHAS
  • Publication number: 20200066692
    Abstract: Package devices (systems and methods for their manufacture) may have an integrated circuit (IC) chip mounted on a top surface of a package substrate of and IC package, and embedded in a mold compound formed onto the top surface. They may also have conductive elements mounted on the top surface of the package substrate, embedded in the mold compound, horizontally disposed at a first vertical sidewall of the package device, and having vertical contact pads exposed at the first vertical sidewall. Conductor material traces of the IC package may electrically couple contacts of the chip to the conductive elements. Traces of the IC package may also electrically couple contacts of the chip to bottom surface contacts of the IC package. The vertical contact pads provide a shorter signal path to another device having vertically mounted surface contacts or opposing contact pads, thus improving signaling to the other device.
    Type: Application
    Filed: December 14, 2016
    Publication date: February 27, 2020
    Applicant: Intel IP Corporation
    Inventors: Andreas WOLTER, Bernd WAIDHAS, Georg SEIDEMANN, Klaus REINGRUBER, Thomas WAGNER
  • Patent number: 10553538
    Abstract: Semiconductor packages having variable redistribution layer thicknesses are described. In an example, a semiconductor package includes a redistribution layer on a dielectric layer, and the redistribution layer includes first conductive traces having a first thickness and second conductive traces having a second thickness. The first thickness may be different than the second thickness, e.g., the first thickness may be less than the second thickness.
    Type: Grant
    Filed: October 4, 2018
    Date of Patent: February 4, 2020
    Assignee: Intel Corporation
    Inventors: Klaus J├╝rgen Reingruber, Sven Albers, Christian Georg Geissler, Georg Seidemann, Bernd Waidhas, Thomas Wagner, Marc Dittes