Abstract: Embodiments disclosed herein include electronic packages with conformal shields and methods of forming such packages. In an embodiment, the electronic package comprises a die having a first surface, a second surface opposite the first surface, and sidewall surfaces. A redistribution layer is over the first surface of the die, and the redistribution layer comprises a first conductive layer. In an embodiment, an under ball metallization (UBM) layer is over the redistribution layer, and a conductive shield is over the sidewall surfaces of the die and the second surface of the die. In an embodiment, the conductive shield is electrically coupled to the UBM layer.

Abstract: Embodiments disclosed herein include electronic package and methods of forming such packages. In an embodiment, an electronic package comprises a mold layer and a first die embedded in the mold layer. In an embodiment, the first die comprises first pads at a first pitch and second pads at a second pitch. In an embodiment, the electronic package further comprises a second die embedded in the mold layer, where the second die comprises third pads at the first pitch and fourth pads at the second pitch. In an embodiment, a bridge die is embedded in the mold layer, and the bridge die electrically couples the second pads to the fourth pads.

Abstract: A semiconductor device and method of including peripheral devices into a package is disclosed. In one example, a peripheral device includes a passive device such as a capacitor or an inductor. Examples are shown that include a peripheral device that is substantially the same thickness as a die or a die assembly. Examples are further shown that use this configuration in a fan out process to form semiconductor devices.

Abstract: A printed wiring-board island relieves added complexity to a printed circuit board. The printed wiring-board island creates an island form factor in the printed circuit board. Coupling of a semiconductive device package to the printed wiring-board island includes a ball-grid array. The ball-grid array can at least partially penetrate the printed wiring-board island.

Abstract: Embodiments of a microelectronic assembly comprise a first integrated circuit (IC) die having first bond-pads on a first surface; an organic dielectric material in contact with the first surface; second bond-pads on a second surface of the organic dielectric material opposite to the first surface; through-dielectric vias (TDVs) in the dielectric material between the first bond-pads and the second bond-pads, wherein the TDVs are in direct contact with the first bond-pads and the second bond-pads; a second IC die embedded in the organic dielectric material and coupled to the first bond-pads by first interconnects; and a package substrate coupled to the second bond-pads by second interconnects.

Abstract: Embodiments include semiconductor packages and a method of forming the semiconductor packages. A semiconductor package includes a mold over and around a first die and a first via. The semiconductor package has a conductive pad of a first redistribution layer disposed on a top surface of the first die and/or a top surface of the mold. The semiconductor package includes a second die having a solder ball coupled to a die pad on a bottom surface of the second die, where the solder ball of the second die is coupled to the first redistribution layer. The first redistribution layer couples the second die to the first die, where the second die has a first edge and a second edge, and where the first edge is positioned within a footprint of the first die and the second edge is positioned outside the footprint of the first die.

Abstract: A die package comprises a semiconductor die comprising a first face, a second face on an opposing second side, an active layer located between the first face and the second face, a first electrical pathway between the first face and the active layer, a second electrical pathway between the second face and the active layer, a first contact pad coupled to the first face and electrically connected to the first electrical pathway, and a second contact pad coupled to the second face and electrically connected to the second electrical pathway. In an example, the first electrical pathway is configured to transmit one or more signals between the first contact pad and the active layer and the second electrical pathway is configured to transmit electrical power between the second contact pad and the active layer.

Abstract: Embodiments herein relate to systems, apparatuses, techniques or processes related to packages that are fully or partially encapsulated in a mold material, with one or more grooves in the mold material to reduce failure in the package during operation. In embodiments, the grooves will allow greater flexibility within the body of the package as it experiences thermo-mechanical stress during operation and will reduce stresses that may be placed on internal components such as chips or bridges in the package, as well as stresses that may be placed on interconnects of the package that are coupled to a substrate. Other embodiments may be described and/or claimed.

Abstract: Embodiments herein relate to systems, apparatuses, techniques, or processes directed to semiconductor packages that include a glass interposer that includes electrically conductive through glass vias that extend through the interposer. One or more dies may be hybrid bonded to a first side of the glass interposer. In embodiments, the second side of the glass interposer may include a redistribution layer that is electrically coupled with the one or more dies through the through glass vias. Other embodiments may be described and/or claimed.

Abstract: Disclosed herein are microelectronic packages having thermally conductive layers and methods for manufacturing the same. The microelectronics packages may include a substrate and a plurality of dies connected to the substrate and/or each other to form a die stack. The dies may have a perimeter. A thermally conductive layer may be located in between the respective dies. The thermally conductive layers may extend past at least a portion of the perimeters, thereby providing enhanced cooling of the die stack.

Abstract: Disclosed herein are microelectronics packages that include thermal pillars for at least localized extraction of generated heat and methods for manufacturing the same. The microelectronics packages may include a substrate and a plurality of dies stacked on the substrate with at least one of the plurality of dies connected to the substrate. A heat spreader may be located proximate at least a portion of the plurality of dies. Respective thermal pillars from a plurality of thermal pillars may extend from at least one of the plurality dies to the heat spreader. Each of the plurality of thermal pillars may define a respective pathway from at least one of the plurality of dies to the heat spreader.

Abstract: An electronic system has a printed circuit board and a substrate. The substrate has two sides, a top and bottom. At least one memory unit is connected to the bottom side of the substrate and at least one processor is connected to the top side of the substrate. The memory is connected to the processor with interconnects that pass through the substrate.

Abstract: A semiconductor package comprises a package substrate comprised of comprised of layers of a first material. The semiconductor package includes an integrated circuit (IC) attached to the substrate at a first surface of the IC through a plurality of vias. The semiconductor package includes at least one interface layer comprised of an interface material different from the first material and sealed from exposure to air. The interface material can comprise a moisture-sensitive nonconductive material and can be disposed within the package substrate or between the first surface of the IC and the package substrate, among other locations. Other systems, apparatuses and methods are described.

Abstract: Disclosed herein are microelectronic assemblies, as well as related apparatuses and methods. In some embodiments, a microelectronic assembly may include a substrate, including a core and a stiffener in the core, wherein the stiffener is along a perimeter of the core; and a die electrically coupled to the substrate.

Abstract: Disclosed herein are microelectronic assemblies, as well as related apparatuses and methods. In some embodiments, a microelectronic assembly may include a die having a first conductive contact on a surface; a substrate having a second conductive contact on a surface; and an interconnect electrically coupling the first conductive contact of the die and the second conductive contact of the substrate, wherein the interconnect includes a portion of a nanowire on the second conductive contact and an intermetallic compound (IMC) surrounding at least a portion of the nanowire on the second conductive contact.

Abstract: Embodiments of a microelectronic assembly comprises a first layer, a second layer and a third layer in a stack; a package substrate in the first layer, the package substrate comprising a metallic via structure; a first integrated circuit (IC) die surrounded by an organic dielectric material in the second layer, the first IC die coupled to the package substrate; a second IC die in the third layer, the second IC die coupled to the first IC die; and a third IC die in the third layer, the third IC die coupled to the first IC die. An electrically conductive pathway in the first IC die electrically couples the third IC die and the second IC die, and the first IC die is coupled to the package substrate with a thermally conductive material in contact with the metallic via structure in the package substrate.

Abstract: Disclosed herein are microelectronic assemblies, as well as related apparatuses and methods. In some embodiments, a microelectronic assembly may include a substrate; and a microelectronic subassembly electrically coupled to the substrate by interconnects, the microelectronic subassembly including an interposer having a surface; a first die electrically coupled to the surface of the interposer; a second die electrically coupled to the surface of the interposer; and a stiffener ring coupled to the surface of the interposer along the perimeter of the interposer.

Abstract: Disclosed herein are microelectronic assemblies, as well as related apparatuses and methods. In some embodiments, a microelectronic assembly may include a substrate having a first surface and an opposing second surface; a die electrically coupled to the second surface of the substrate; and a stiffener attached to the first surface of the substrate configured to mitigate warpage of the die.

Abstract: A semiconductor package includes a first semiconductor die, a semiconductor device comprising a second semiconductor die, and one or more wire bond structures. The wire bond structure includes a bond interface portion. The wire bond structure is arranged next to the first semiconductor die. The first semiconductor die and the bond interface portion of the wire bond structure are arranged at the same side of the semiconductor device. An interface contact structure of the semiconductor device is electrically connected to the wire bond structure.

Abstract: A microelectronic assembly is provided, comprising: an interposer having a first side and a second side opposite to the first side; a plurality of integrated circuit (IC) dies in a plurality of layers on the first side of the interposer, the plurality of IC dies being encased by a dielectric material; a package substrate on the second side of the interposer; a plurality of conductive vias through the plurality of layers; and redistribution layers adjacent to the layers in the plurality of layers, at least some of the redistribution layers comprising conductive traces coupling the conductive vias to the IC dies.