Abstract: A die package comprises a semiconductor die comprising a first face, a second face on an opposing second side, an active layer located between the first face and the second face, a first electrical pathway between the first face and the active layer, a second electrical pathway between the second face and the active layer, a first contact pad coupled to the first face and electrically connected to the first electrical pathway, and a second contact pad coupled to the second face and electrically connected to the second electrical pathway. In an example, the first electrical pathway is configured to transmit one or more signals between the first contact pad and the active layer and the second electrical pathway is configured to transmit electrical power between the second contact pad and the active layer.

Abstract: Bridge die interposer packages, and related apparatuses, systems, and techniques are discussed. An interposer package includes a bridge die having a routing structure to interconnect multiple integrated circuit (IC) dies of the package. Power is provided to the IC dies by a mesh power supply metallization and a mesh ground metallization that extend from outside a perimeter of the bridge die to within the perimeter and over the routing structure. The bridge die may be absent through silicon vias (TSVs) and may be hanging such that it is exposed at the bottom of the package.

Abstract: Microelectronic assemblies with organic interposers and fanout routing dies are described. In one example, an assembly includes an interposer with one or more redistribution layers (RDLs) and first conductive contacts with a first pitch on a first side of the interposer, and a die (e.g., fanout routing die) with two or more backend of line (BEOL) interconnect layers. The assembly may further include second conductive contacts with the first pitch coupled with the first conductive contacts, and third conductive contacts with a second pitch that is smaller than the first pitch, where one of the third conductive contacts is coupled with a conductive interconnect in the RDLs of the interposer.

Abstract: An apparatus is provided which comprises: an interposer comprising traces and conductive contacts on a first interposer surface and a second interposer surface opposite the first interposer surface, a computing device coupled with contacts on the first interposer surface, a first memory array coupled with contacts on the first interposer surface, and a second memory array embedded between the first interposer surface and the second interposer surface, the second memory array inverted in orientation relative to the first memory array, the second memory array directly coupled through traces in the interposer with the first memory array and the computing device. Other embodiments are also disclosed and claimed.

Abstract: Microelectronic assemblies, related devices and methods, are disclosed herein. In some embodiments, a microelectronic assembly may include a die surrounded by an insulating material, the die having a first conductive contact at a first surface and a second conductive contact at a second surface opposite the first surface, a first redistribution layer (RDL), on the first surface of the die, including a first conductive pathway through a first dielectric material electrically coupled to the first conductive contact of the die by a first solderless metal-metal interconnect; and a second RDL, on second surface of the die, including a second conductive pathway through a second dielectric material electrically coupled to the second conductive contact of the die by a second solderless metal-metal interconnect, wherein a thickness of the die is between 20 microns and 45 microns. In some embodiments, a thickness of the die is between 60 microns and 75 microns.

Abstract: Microelectronic assemblies, related devices and methods, are disclosed herein. In some embodiments, a microelectronic assembly may include a first layer with first conductive pillars and second conductive pillars through an insulating material; a redistribution layer (RDL), on the first layer, having signal conductive pathways and ground conductive pathways through a dielectric material, wherein the signal conductive pathways are electrically coupled to the first conductive pillars and the ground conductive pathways are electrically coupled to the second conductive pillars; and a second layer, on the RDL, having a structural component having a surface facing towards the RDL, wherein the surface of the structural component includes a conductive reference plane electrically coupled to the ground conductive pathways in the RDL, and wherein at least some of the first conductive pillars are within a footprint of the structural component.

Abstract: Embodiments of a microelectronic assembly comprises a first layer, a second layer and a third layer in a stack; a package substrate in the first layer, the package substrate comprising a metallic via structure; a first integrated circuit (IC) die surrounded by an organic dielectric material in the second layer, the first IC die coupled to the package substrate; a second IC die in the third layer, the second IC die coupled to the first IC die; and a third IC die in the third layer, the third IC die coupled to the first IC die. An electrically conductive pathway in the first IC die electrically couples the third IC die and the second IC die, and the first IC die is coupled to the package substrate with a thermally conductive material in contact with the metallic via structure in the package substrate.

Abstract: Embodiments disclosed herein include electronic package and methods of forming such packages. In an embodiment, an electronic package comprises a mold layer and a first die embedded in the mold layer. In an embodiment, the first die comprises first pads at a first pitch and second pads at a second pitch. In an embodiment, the electronic package further comprises a second die embedded in the mold layer, where the second die comprises third pads at the first pitch and fourth pads at the second pitch. In an embodiment, a bridge die is embedded in the mold layer, and the bridge die electrically couples the second pads to the fourth pads.

Abstract: A microelectronic assembly is provided, comprising: an interposer having a first side and a second side opposite to the first side; a plurality of integrated circuit (IC) dies in a plurality of layers on the first side of the interposer, the plurality of IC dies being encased by a dielectric material; a package substrate on the second side of the interposer; a plurality of conductive vias through the plurality of layers; and redistribution layers adjacent to the layers in the plurality of layers, at least some of the redistribution layers comprising conductive traces coupling the conductive vias to the IC dies.

Abstract: Embodiments disclosed herein include electronic package and methods of forming such packages. In an embodiment, an electronic package comprises a mold layer and a first die embedded in the mold layer. In an embodiment, the first die comprises first pads at a first pitch and second pads at a second pitch. In an embodiment, the electronic package further comprises a second die embedded in the mold layer, where the second die comprises third pads at the first pitch and fourth pads at the second pitch. In an embodiment, a bridge die is embedded in the mold layer, and the bridge die electrically couples the second pads to the fourth pads.

Abstract: A system-in-package apparatus includes a semiconductive bridge that uses bare-die pillars to couple with a semiconductive device such as a processor die. The apparatus achieves a thin form factor.

Abstract: IC chip package routing structures including a metal-insulator-metal (MIM) capacitor integrated with redistribution layers. An active side of an IC chip may be electrically coupled to the redistribution layers through first-level interconnects. The redistribution layers terminate at interfaces suitable for coupling a package to a host component through second-level interconnects. The MIM capacitor structure may comprise materials suitable for high temperature processing, for example of 350° C., or more. The MIM capacitor structure may therefore be fabricated over a host substrate using higher temperature processing. The redistribution layers and MIM capacitor may then be embedded within package dielectric material(s) using lower temperature processing. An IC chip may be attached to the package routing structure, and the package then separated from the host substrate for further assembly to a host component.

Abstract: A semiconductor device and method of including peripheral devices into a package is disclosed. In one example, a peripheral device includes a passive device such as a capacitor or an inductor. Examples are shown that include a peripheral device that is substantially the same thickness as a die or a die assembly. Examples are further shown that use this configuration in a fan out process to form semiconductor devices.

Abstract: IC devices including BPRs with integrated decoupling capacitance are disclosed. An example IC device includes a first layer comprising a transistor and a support structure adjoining the first layer. The support structure includes BPRs, which are power rails buried in the support structure, and a decoupling capacitor based on the BPRs. The conductive cores of the BPRs are the electrodes of the decoupling capacitor. The dielectric barriers of the BPRs can be the dielectric of the decupling capacitor. The dielectric of the decupling capacitor may also include a dielectric element between the BPRs. Additionally or alternatively, the IC device includes another decoupling capacitor at the backside of the support structure. The other decoupling capacitor is coupled to the BPRs and can provide additional decoupling capacitance for stabilizing power supply facilitated by the BPRs.

Abstract: A system-in-package apparatus includes a semiconductive bridge that uses bare-die pillars to couple with a semiconductive device such as a processor dic. The apparatus achieves a thin form factor.

Abstract: A system-in-package apparatus includes a semiconductive bridge that uses bare-die pillars to couple with a semiconductive device such as a processor die. The apparatus achieves a thin form factor.

Abstract: A system-in-package apparatus includes a semiconductive bridge that uses bare-die pillars to couple with a semiconductive device such as a processor die. The apparatus achieves a thin form factor.

Abstract: Embodiments disclosed herein include electronic packages with conformal shields and methods of forming such packages. In an embodiment, the electronic package comprises a die having a first surface, a second surface opposite the first surface, and sidewall surfaces. A redistribution layer is over the first surface of the die, and the redistribution layer comprises a first conductive layer. In an embodiment, an under ball metallization (UBM) layer is over the redistribution layer, and a conductive shield is over the sidewall surfaces of the die and the second surface of the die. In an embodiment, the conductive shield is electrically coupled to the UBM layer.

Abstract: Microelectronic assemblies, related devices and methods, are disclosed herein. In some embodiments, a microelectronic assembly may include a package substrate, having a surface, including a first conductive pathway electrically coupled to a power source; an insulating material on the surface of the package substrate; a first microelectronic component, having a first surface facing the package substrate and an opposing second surface, embedded in the insulating material; a second microelectronic component, having a first surface facing the package substrate and an opposing second surface, embedded in the insulating material; a redistribution layer on the insulating material including a second conductive pathway electrically coupled to the second surface of the second microelectronic component and the second surface of the first microelectronic component; and a wire bond electrically coupling the first and the second conductive pathways.

Abstract: A semiconductor device and method of including peripheral devices into a package is disclosed. In one example, a peripheral device includes a passive device such as a capacitor or an inductor. Examples are shown that include a peripheral device that is substantially the same thickness as a die or a die assembly. Examples are further shown that use this configuration in a fan out process to form semiconductor devices.