Patents by Inventor Bernd Zippelius

Bernd Zippelius has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20240072122
    Abstract: A semiconductor device includes a transistor including transistor cells. Each transistor cells has a gate electrode arranged in gate trenches formed in a first portion of a silicon carbide substrate and extending in a first horizontal direction, a source region, a channel region, and a current-spreading region. The source region, channel region, and at least part of the current-spreading region are arranged in ridges patterned by the gate trenches. The transistor cells further include a body contact portion of the second conductivity type arranged in a second portion of the silicon carbide substrate and electrically connected to the channel region. The transistor cells further include a shielding region of the second conductivity type. A first portion of the shielding region is arranged below the gate trenches, respectively, and a second portion of the shielding region is arranged adjacent to a sidewall of the gate trenches, respectively.
    Type: Application
    Filed: August 3, 2023
    Publication date: February 29, 2024
    Inventors: Michael Hell, Rudolf Elpelt, Caspar Leendertz, Bernd Zippelius, Dethard Peters
  • Patent number: 11462611
    Abstract: A semiconductor device includes gate trenches formed in a SiC substrate and extending lengthwise in parallel in a first direction. A trench interval which defines a space between adjacent gate trenches extends in a second direction perpendicular to the first direction. Source regions of a first conductivity type formed in the SiC substrate occupy a first part of the space between adjacent gate trenches. Body regions of a second conductivity type opposite the first conductivity type formed in the SiC substrate and below the source regions occupy a second part of the space between adjacent gate trenches. Body contact regions of the second conductivity type formed in the SiC substrate occupy a third part of the space between adjacent gate trenches. Shielding regions of the second conductivity type formed deeper in the SiC substrate than the body regions adjoin a bottom of at least some of the gate trenches.
    Type: Grant
    Filed: December 4, 2020
    Date of Patent: October 4, 2022
    Assignee: Infineon Technologies AG
    Inventors: Thomas Aichinger, Wolfgang Bergner, Paul Ellinghaus, Rudolf Elpelt, Romain Esteve, Florian Grasse, Caspar Leendertz, Shiqin Niu, Dethard Peters, Ralf Siemieniec, Bernd Zippelius
  • Patent number: 11211303
    Abstract: An embodiment of a semiconductor device includes a semiconductor body having a first main surface. The semiconductor body includes an active device area and an edge termination area at least partly surrounding the active device area. The semiconductor device further includes a contact electrode on the first main surface and electrically connected to the active device area. The semiconductor device further includes a passivation structure on the edge termination area and laterally extending into the active device area. The semiconductor device further includes an encapsulation structure on the passivation structure and covering a first edge of the passivation structure above the contact electrode.
    Type: Grant
    Filed: December 3, 2019
    Date of Patent: December 28, 2021
    Assignee: Infineon Technologies AG
    Inventors: Jens Peter Konrath, Jochen Hilsenbeck, Dethard Peters, Paul Salmen, Tobias Schmidutz, Vice Sodan, Christian Stahlhut, Juergen Steinbrenner, Bernd Zippelius
  • Patent number: 11145755
    Abstract: A semiconductor component includes a SiC semiconductor body having an active region and an edge termination structure at least partly surrounding the active region. A drift zone of a first conductivity type is formed in the SiC semiconductor body. The edge termination structure includes: a first doped region of a second conductivity type between a first surface of the SiC semiconductor body and the drift zone, the first doped region at least partly surrounding the active region and being spaced apart from the first surface; a plurality of second doped regions of the second conductivity type between the first surface and the first doped region; and third doped regions of the first conductivity type separating adjacent second doped regions of the plurality of second doped regions from one another in a lateral direction.
    Type: Grant
    Filed: November 20, 2018
    Date of Patent: October 12, 2021
    Assignee: Infineon Technologies AG
    Inventors: Larissa Wehrhahn-Kilian, Rudolf Elpelt, Roland Rupp, Ralf Siemieniec, Bernd Zippelius
  • Patent number: 11063144
    Abstract: A semiconductor component includes a SiC semiconductor body. A drift zone of a first conductivity type and a semiconductor region are formed in the SiC semiconductor body. Barrier structures extending from the semiconductor region into the drift zone differ from the gate structures.
    Type: Grant
    Filed: March 22, 2019
    Date of Patent: July 13, 2021
    Assignee: Infineon Technologies AG
    Inventors: Roland Rupp, Larissa Wehrhahn-Kilian, Bernd Zippelius
  • Publication number: 20210118986
    Abstract: A semiconductor device includes gate trenches formed in a SiC substrate and extending lengthwise in parallel in a first direction. A trench interval which defines a space between adjacent gate trenches extends in a second direction perpendicular to the first direction. Source regions of a first conductivity type formed in the SiC substrate occupy a first part of the space between adjacent gate trenches. Body regions of a second conductivity type opposite the first conductivity type formed in the SiC substrate and below the source regions occupy a second part of the space between adjacent gate trenches. Body contact regions of the second conductivity type formed in the SiC substrate occupy a third part of the space between adjacent gate trenches. Shielding regions of the second conductivity type formed deeper in the SiC substrate than the body regions adjoin a bottom of at least some of the gate trenches.
    Type: Application
    Filed: December 4, 2020
    Publication date: April 22, 2021
    Inventors: Thomas Aichinger, Wolfgang Bergner, Paul Ellinghaus, Rudolf Elpelt, Romain Esteve, Florian Grasse, Caspar Leendertz, Shiqin Niu, Dethard Peters, Ralf Siemieniec, Bernd Zippelius
  • Patent number: 10985248
    Abstract: Embodiments of SiC devices and corresponding methods of manufacture are provided. In some embodiments, the SiC device has shielding regions at the bottom of some gate trenches and non-linear junctions formed with the SiC material at the bottom of other gate trenches. In other embodiments, the SiC device has the shielding regions at the bottom of the gate trenches and arranged in rows which run in a direction transverse to a lengthwise extension of the trenches. In still other embodiments, the SiC device has the shielding regions and the non-linear junctions, and wherein the shielding regions are arranged in rows which run in a direction transverse to a lengthwise extension of the trenches.
    Type: Grant
    Filed: March 15, 2019
    Date of Patent: April 20, 2021
    Assignee: Infineon Technologies AG
    Inventors: Caspar Leendertz, Romain Esteve, Anton Mauder, Andreas Meiser, Bernd Zippelius
  • Patent number: 10896952
    Abstract: A semiconductor device includes gate trenches formed in a SiC substrate and extending lengthwise in parallel in a first direction. A trench interval which defines a space between adjacent gate trenches extends in a second direction perpendicular to the first direction. Source regions of a first conductivity type formed in the SiC substrate occupy a first part of the space between adjacent gate trenches. Body regions of a second conductivity type opposite the first conductivity type formed in the SiC substrate and below the source regions occupy a second part of the space between adjacent gate trenches. Body contact regions of the second conductivity type formed in the SiC substrate occupy a third part of the space between adjacent gate trenches. Shielding regions of the second conductivity type formed deeper in the SiC substrate than the body regions adjoin a bottom of at least some of the gate trenches.
    Type: Grant
    Filed: February 21, 2020
    Date of Patent: January 19, 2021
    Assignee: Infineon Technologies AG
    Inventors: Thomas Aichinger, Wolfgang Bergner, Paul Ellinghaus, Rudolf Elpelt, Romain Esteve, Florian Grasse, Caspar Leendertz, Shiqin Niu, Dethard Peters, Ralf Siemieniec, Bernd Zippelius
  • Patent number: 10861964
    Abstract: A semiconductor device includes a drift zone formed in a semiconductor portion. In a transition section of the semiconductor portion a vertical extension of the semiconductor portion decreases from a first vertical extension to a second vertical extension. A junction termination zone of a conductivity type complementary to a conductivity type of the drift zone is formed between a first surface of the semiconductor portion and the drift zone and includes a tapering portion in the transition section. In the tapering portion a vertical extension of the junction termination zone decreases from a maximum vertical extension to zero within a lateral width of at least twice the maximum vertical extension.
    Type: Grant
    Filed: October 26, 2018
    Date of Patent: December 8, 2020
    Assignee: Infineon Technologies AG
    Inventors: Roland Rupp, Rudolf Elpelt, Reinhold Schoerner, Larissa Wehrhahn-Kilian, Bernd Zippelius
  • Patent number: 10700182
    Abstract: By using at least one of a processor device and model transistor cells, a set of design parameters for at least one of a transistor cell and a drift structure of a wide band-gap semiconductor device is determined, wherein an on state failure-in-time rate and an off state failure-in-time rate of a gate dielectric of the transistor cell are within a same order of magnitude for a predefined on-state gate-to-source voltage, a predefined off-state gate-to-source voltage, and a predefined off-state drain-to-source voltage.
    Type: Grant
    Filed: May 14, 2018
    Date of Patent: June 30, 2020
    Assignee: Infineon Technologies AG
    Inventors: Thomas Aichinger, Wolfgang Bergner, Romain Esteve, Daniel Kueck, Dethard Peters, Ralf Siemieniec, Bernd Zippelius
  • Publication number: 20200194544
    Abstract: A semiconductor device includes gate trenches formed in a SiC substrate and extending lengthwise in parallel in a first direction. A trench interval which defines a space between adjacent gate trenches extends in a second direction perpendicular to the first direction. Source regions of a first conductivity type formed in the SiC substrate occupy a first part of the space between adjacent gate trenches. Body regions of a second conductivity type opposite the first conductivity type formed in the SiC substrate and below the source regions occupy a second part of the space between adjacent gate trenches. Body contact regions of the second conductivity type formed in the SiC substrate occupy a third part of the space between adjacent gate trenches. Shielding regions of the second conductivity type formed deeper in the SiC substrate than the body regions adjoin a bottom of at least some of the gate trenches.
    Type: Application
    Filed: February 21, 2020
    Publication date: June 18, 2020
    Inventors: Thomas Aichinger, Wolfgang Bergner, Paul Ellinghaus, Rudolf Elpelt, Romain Esteve, Florian Grasse, Caspar Leendertz, Shiqin Niu, Dethard Peters, Ralf Siemieniec, Bernd Zippelius
  • Publication number: 20200185297
    Abstract: An embodiment of a semiconductor device includes a semiconductor body having a first main surface. The semiconductor body includes an active device area and an edge termination area at least partly surrounding the active device area. The semiconductor device further includes a contact electrode on the first main surface and electrically connected to the active device area. The semiconductor device further includes a passivation structure on the edge termination area and laterally extending into the active device area. The semiconductor device further includes an encapsulation structure on the passivation structure and covering a first edge of the passivation structure above the contact electrode.
    Type: Application
    Filed: December 3, 2019
    Publication date: June 11, 2020
    Inventors: Jens Peter Konrath, Jochen Hilsenbeck, Dethard Peters, Paul Salmen, Tobias Schmidutz, Vice Sodan, Christian Stahlhut, Juergen Steinbrenner, Bernd Zippelius
  • Publication number: 20200161433
    Abstract: Embodiments of SiC devices and corresponding methods of manufacture are provided. In some embodiments, the SiC device has shielding regions at the bottom of some gate trenches and non-linear junctions formed with the SiC material at the bottom of other gate trenches. In other embodiments, the SiC device has the shielding regions at the bottom of the gate trenches and arranged in rows which run in a direction transverse to a lengthwise extension of the trenches. In still other embodiments, the SiC device has the shielding regions and the non-linear junctions, and wherein the shielding regions are arranged in rows which run in a direction transverse to a lengthwise extension of the trenches.
    Type: Application
    Filed: March 15, 2019
    Publication date: May 21, 2020
    Inventors: Caspar Leendertz, Romain Esteve, Anton Mauder, Andreas Meiser, Bernd Zippelius
  • Patent number: 10586845
    Abstract: According to an embodiment of a semiconductor device, the device includes gate trenches formed in a SiC substrate and extending lengthwise in parallel in a first direction. Rows of source regions of a first conductivity type are formed in the SiC substrate and extend lengthwise in parallel in a second direction which is transverse to the first direction. Rows of body regions of a second conductivity type opposite the first conductivity type are formed in the SiC substrate below the rows of source regions. Rows of body contact regions of the second conductivity type are formed in the SiC substrate. The rows of body contact regions extend lengthwise in parallel in the second direction. First shielding regions of the second conductivity type are formed deeper in the SiC substrate than the rows of body regions.
    Type: Grant
    Filed: November 16, 2018
    Date of Patent: March 10, 2020
    Assignee: Infineon Technologies AG
    Inventors: Thomas Aichinger, Wolfgang Bergner, Paul Ellinghaus, Rudolf Elpelt, Romain Esteve, Florian Grasse, Caspar Leendertz, Shiqin Niu, Dethard Peters, Ralf Siemieniec, Bernd Zippelius
  • Patent number: 10541325
    Abstract: In termination regions of a silicon carbide substrate field zones are formed by ion implantation. By laterally modulating a distribution of dopants entering the silicon carbide substrate by the ion implantation, a horizontal net dopant distribution in the field zones is set to fall from a maximum net dopant concentration Nmax to Nmax/e within at least 200 nm, with e representing Euler's number. The field zones form first pn junctions with a drift layer.
    Type: Grant
    Filed: October 26, 2018
    Date of Patent: January 21, 2020
    Assignee: Infineon Technologies AG
    Inventors: Rudolf Elpelt, Roland Rupp, Reinhold Schoerner, Larissa Wehrhahn-Kilian, Bernd Zippelius
  • Publication number: 20200006544
    Abstract: A semiconductor device includes a silicon carbide body including a transistor cell region and an idle region. The transistor cell region includes transistor cells. The idle region is devoid of transistor cells. The idle region includes a transition region between the transistor cell region and a side surface of the silicon carbide body, a gate pad region, and a diode structure comprising at least one of a merged pin Schottky diode structure or a merged pin heterojunction diode structure in at least one of the transition region or the gate pad region.
    Type: Application
    Filed: June 27, 2019
    Publication date: January 2, 2020
    Inventors: Ralf SIEMIENIEC, Thomas AICHINGER, Wolfgang BERGNER, Romain ESTEVE, Daniel KUECK, Dethard PETERS, Bernd ZIPPELIUS
  • Publication number: 20190296141
    Abstract: A semiconductor component includes a SiC semiconductor body. A drift zone of a first conductivity type and a semiconductor region are formed in the SiC semiconductor body. Barrier structures extending from the semiconductor region into the drift zone differ from the gate structures.
    Type: Application
    Filed: March 22, 2019
    Publication date: September 26, 2019
    Inventors: Roland Rupp, Larissa Wehrhahn-Kilian, Bernd Zippelius
  • Publication number: 20190165159
    Abstract: A semiconductor component includes a SiC semiconductor body having an active region and an edge termination structure at least partly surrounding the active region. A drift zone of a first conductivity type is formed in the SiC semiconductor body. The edge termination structure includes: a first doped region of a second conductivity type between a first surface of the SiC semiconductor body and the drift zone, the first doped region at least partly surrounding the active region and being spaced apart from the first surface; a plurality of second doped regions of the second conductivity type between the first surface and the first doped region; and third doped regions of the first conductivity type separating adjacent second doped regions of the plurality of second doped regions from one another in a lateral direction.
    Type: Application
    Filed: November 20, 2018
    Publication date: May 30, 2019
    Inventors: Larissa Wehrhahn-Kilian, Rudolf Elpelt, Roland Rupp, Ralf Siemieniec, Bernd Zippelius
  • Publication number: 20190131447
    Abstract: In termination regions of a silicon carbide substrate field zones are formed by ion implantation. By laterally modulating a distribution of dopants entering the silicon carbide substrate by the ion implantation, a horizontal net dopant distribution in the field zones is set to fall from a maximum net dopant concentration Nmax to Nmax/e within at least 200 nm, with e representing Euler's number. The field zones form first pn junctions with a drift layer.
    Type: Application
    Filed: October 26, 2018
    Publication date: May 2, 2019
    Inventors: Rudolf Elpelt, Roland Rupp, Reinhold Schoerner, Larissa Wehrhahn-Kilian, Bernd Zippelius
  • Publication number: 20190131446
    Abstract: A semiconductor device includes a drift zone formed in a semiconductor portion. In a transition section of the semiconductor portion a vertical extension of the semiconductor portion decreases from a first vertical extension to a second vertical extension. A junction termination zone of a conductivity type complementary to a conductivity type of the drift zone is formed between a first surface of the semiconductor portion and the drift zone and includes a tapering portion in the transition section. In the tapering portion a vertical extension of the junction termination zone decreases from a maximum vertical extension to zero within a lateral width of at least twice the maximum vertical extension.
    Type: Application
    Filed: October 26, 2018
    Publication date: May 2, 2019
    Inventors: Roland Rupp, Rudolf Elpelt, Reinhold Schoerner, Larissa Wehrhahn-Kilian, Bernd Zippelius