Patents by Inventor Bernhard Egger

Bernhard Egger has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20210279587
    Abstract: A method and an apparatus for generating a code for a neural network operation are disclosed. The method includes receiving information on hardware configured to perform a neural network operation of the neural network, generating, using a processor, a target mapping model mapping the neural network operation on processing elements available to perform the neural network operation based on the information and a structure of the neural network, and generating a code to configure the hardware to perform the neural network operation based on the target mapping model.
    Type: Application
    Filed: March 3, 2021
    Publication date: September 9, 2021
    Applicants: Samsung Electronics Co., Ltd., SNU R&DB FOUNDATION
    Inventors: Bernhard EGGER, Minsu KIM, Hyemi MIN
  • Patent number: 10713095
    Abstract: A method of controlling a multi-core processor includes allocating at least one core of the multi-core processor to at least one process for execution; generating a translation table with respect to the at least one process to translate a logical ID of the at least one core allocated to the at least one process to a physical ID; and controlling the at least one process based on the translation table generated with respect to the at least one process.
    Type: Grant
    Filed: March 27, 2017
    Date of Patent: July 14, 2020
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Donghoon Yoo, Bernhard Egger
  • Patent number: 10503557
    Abstract: A multi-core computing device includes a control core group having first low-level control cores and a processing core group. The control core group allocates work groups for executing an Open Computing Language (OpenCL) kernel to the first low-level control cores and first processing cores among the processing core group. The processing core group performs processing of the work groups allocated by the control core group outputs results of the processing. The control cores are hierarchically grouped.
    Type: Grant
    Filed: October 18, 2017
    Date of Patent: December 10, 2019
    Assignees: SAMSUNG ELECTRONICS CO., LTD., SEOUL NATIONAL UNIVERSITY R&DB FOUNDATION
    Inventors: Bernhard Egger, Su-Rim Oh, Younghyun Cho, Dong-Hoon Yoo
  • Publication number: 20190339760
    Abstract: Provided are computing devices, each including a plurality of cores, and methods of allocating power to the plurality of cores. The computing device includes: a control core group including a plurality of control cores, the control core group configured to allocate a power budget to processing cores according to an energy management policy and state information of the processing cores, and transmit the allocated power budget to at least one of a lower control core and the processing cores; and a processing core group including at least one or more of the processing cores, the processing core group configured to perform computations based on the power budget allocated by the control core group, and transmit state information of the processing cores to the control core group, the state information of the processing cores having been modified based on the computations performed.
    Type: Application
    Filed: July 22, 2019
    Publication date: November 7, 2019
    Applicants: Samsung Electronics Co., Ltd., SEOUL NATIONAL UNIVERSITY R&DB FOUNDATION
    Inventors: Bernhard Egger, Younghyun CHO, Su-Rim Oh, Dong-hoon Yoo
  • Patent number: 10409351
    Abstract: Provided are computing devices, each including a plurality of cores, and methods of allocating power to the plurality of cores. The computing device includes: a control core group including a plurality of control cores, the control core group configured to allocate a power budget to processing cores according to an energy management policy and state information of the processing cores, and transmit the allocated power budget to at least one of a lower control core and the processing cores; and a processing core group including at least one or more of the processing cores, the processing core group configured to perform computations based on the power budget allocated by the control core group, and transmit state information of the processing cores to the control core group, the state information of the processing cores having been modified based on the computations performed.
    Type: Grant
    Filed: October 19, 2017
    Date of Patent: September 10, 2019
    Assignees: Samsung Electronics Co., Ltd., Seoul National University R&DB Foundation
    Inventors: Bernhard Egger, Younghyun Cho, Su-Rim Oh, Dong-hoon Yoo
  • Patent number: 10140247
    Abstract: Methods and apparatuses are provided for compressing configuration data. The configuration data, which includes control data corresponding to at least one processing unit used in each of a plurality of cycles, is stored. A plurality of processing units of a reconfigurable processor is divided into a plurality of groups. The configuration data is partitioned into a plurality of pieces of sub-configuration data. Each piece of sub-configuration data corresponding to a respective one of the plurality of groups. If a plurality of adjacent cycles include identical control data, the configuration data is compressed by deleting control data of all but one of the plurality of adjacent cycles, for each sub-configuration data.
    Type: Grant
    Filed: September 6, 2017
    Date of Patent: November 27, 2018
    Assignees: Samsung Electronics Co., Ltd, Seoul National University R&DB Foundation
    Inventors: Bernhard Egger, Ho-chan Lee, Yeon-bok Lee, Suk-jin Kim
  • Publication number: 20180246554
    Abstract: Provided are computing devices, each including a plurality of cores, and methods of allocating power to the plurality of cores. The computing device includes: a control core group including a plurality of control cores, the control core group configured to allocate a power budget to processing cores according to an energy management policy and state information of the processing cores, and transmit the allocated power budget to at least one of a lower control core and the processing cores; and a processing core group including at least one or more of the processing cores, the processing core group configured to perform computations based on the power budget allocated by the control core group, and transmit state information of the processing cores to the control core group, the state information of the processing cores having been modified based on the computations performed.
    Type: Application
    Filed: October 19, 2017
    Publication date: August 30, 2018
    Applicants: Samsung Electronics Co., Ltd., Seoul National University R&DB Foundation
    Inventors: Bernhard EGGER, Younghyun CHO, Su-Rim OH, Dong-hoon YOO
  • Publication number: 20180181443
    Abstract: A multi-core computing device includes a control core group having first low-level control cores and a processing core group. The control core group allocates work groups for executing an Open Computing Language (OpenCL) kernel to the first low-level control cores and first processing cores among the processing core group. The processing core group performs processing of the work groups allocated by the control core group outputs results of the processing. The control cores are hierarchically grouped.
    Type: Application
    Filed: October 18, 2017
    Publication date: June 28, 2018
    Applicant: SEOUL NATIONAL UNIVERSITY R&DB FOUNDATION
    Inventors: BERNHARD EGGER, Su-Rim Oh, Younghyun Cho, Dong-Hoon Yoo
  • Patent number: 9959191
    Abstract: A dynamic library profiling method and a dynamic library profiling system including writing a first break point instruction at a start address of a dynamic library function, recording a first event count value that is a process performance management unit (PMU) count when a target process executes the first break point instruction, writing a second break point instruction to a return address of the dynamic library function, and calculating a PMU count generated in a processor core while the dynamic library function is executed, by comparing the recorded first event count value with a second event count value that is a process PMU count when the target process executes the second break point instruction, wherein the process PMU count is a cumulative value of PMU counts generated in the processor core while the target process is executed.
    Type: Grant
    Filed: November 22, 2013
    Date of Patent: May 1, 2018
    Assignees: SAMSUNG ELECTRONICS CO., LTD., SEOUL NATIONAL UNIVERSITY R&DB FOUNDATION
    Inventors: Min-Ju Lee, Bernhard Egger, Jae-jin Lee, Young-Lak Kim, Hong-Gyu Kim, Hong-June Kim
  • Publication number: 20180067895
    Abstract: Methods and apparatuses are provided for compressing configuration data. The configuration data, which includes control data corresponding to at least one processing unit used in each of a plurality of cycles, is stored. A plurality of processing units of a reconfigurable processor is divided into a plurality of groups. The configuration data is partitioned into a plurality of pieces of sub-configuration data. Each piece of sub-configuration data corresponding to a respective one of the plurality of groups. If a plurality of adjacent cycles include identical control data, the configuration data is compressed by deleting control data of all but one of the plurality of adjacent cycles, for each sub-configuration data.
    Type: Application
    Filed: September 6, 2017
    Publication date: March 8, 2018
    Inventors: Bernhard EGGER, Ho-chan LEE, Yeon-bok LEE, Suk-jin KIM
  • Publication number: 20170277571
    Abstract: A method of controlling a multi-core processor includes allocating at least one core of the multi-core processor to at least one process for execution; generating a translation table with respect to the at least one process to translate a logical ID of the at least one core allocated to the at least one process to a physical ID; and controlling the at least one process based on the translation table generated with respect to the at least one process.
    Type: Application
    Filed: March 27, 2017
    Publication date: September 28, 2017
    Applicants: Samsung Electronics Co., Ltd., Seoul National University R&DB Foundation
    Inventors: Donghoon YOO, Bernhard EGGER
  • Patent number: 9727528
    Abstract: Provided is a reconfigurable processor capable of reducing the routing processing time of routing nodes by driving the routing nodes at a greater frequency than a driving frequency of the processing elements. The reconfigurable processor includes one or more processing elements configured to be driven at a first driving frequency, and one or more routing nodes configured to be provided on paths that are formed between the processing elements, and to be driven at a second driving frequency that is greater than the first driving frequency.
    Type: Grant
    Filed: July 7, 2011
    Date of Patent: August 8, 2017
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Bernhard Egger, Taisong Jin, Won-Sub Kim
  • Patent number: 9411582
    Abstract: An apparatus for processing an invalid operation in a prologue and/or an epilogue of a loop includes a register file including a first region for storing a data validity value indicating whether data is valid or invalid, and a second region for storing the data; and a functional unit configured to determine whether an operation is valid or invalid based on a value of a first region of each of one or more input sources received from the register file, and output a destination including a value based on the value of the first region of each of the input sources.
    Type: Grant
    Filed: March 15, 2013
    Date of Patent: August 9, 2016
    Assignees: Samsung Electronics Co., Ltd., Seoul Electronics University R&DB Foundation
    Inventors: Seong-Hun Jeong, Bernhard Egger, Won-Sub Kim
  • Patent number: 9342480
    Abstract: An apparatus and method for generating a very long instruction word (VLIW) command that supports predicated execution, and a VLIW processor and method for processing a VLIW are provided herein. The VLIW command includes an instruction bundle formed of a plurality of instructions to be executed in parallel and a single value indicating predicated execution, and is generated using the apparatus and method for generating a VLIW command. The VLIW processor decodes the instruction bundle and executes the instructions, which are included in the decoded instruction bundle, in parallel, according to the value indicating predicated execution.
    Type: Grant
    Filed: October 28, 2013
    Date of Patent: May 17, 2016
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Bernhard Egger, Soo-jung Ryu, Dong-hoon Yoo, Il-hyun Park
  • Patent number: 9304967
    Abstract: Provided is a reconfigurable processor that may process a first type of operation in first mode using a first group of functional units, and process a second type of operation in second mode using a second group of functional units. The reconfigurable processor may selectively supply power to either the first group or the second group, in response to a mode-switch signal or a mode-switch instruction.
    Type: Grant
    Filed: August 19, 2011
    Date of Patent: April 5, 2016
    Assignees: Samsung Electronics Co., Ltd., POSTECH ACADEMY-INDUSTRY FOUNDATION
    Inventors: Sung-Joo Yoo, Yeon-Gon Cho, Bernhard Egger, Won-Sub Kim, Hee-Jin Ahn
  • Patent number: 9286074
    Abstract: An instruction compressing apparatus and method for a parallel processing computer such as a very long instruction word (VLIW) computer, are provided. The instruction compressing apparatus includes a bundle code generating unit, an instruction compressing unit, and an instruction converting unit. The bundle code generating unit may generate a bundle code in response to an input of instructions to be compressed. The bundle code may indicate whether a current instruction group is terminated, and also whether an instruction group following the current instruction group is a no-operation (NOP) instruction group. The instruction compressing unit may remove a NOP instruction and/or a NOP instruction group from the input instructions according to the generated bundle code. The instruction converting unit may include the generated bundle code in the remaining instructions which have not been removed by the instruction compressing unit.
    Type: Grant
    Filed: October 26, 2010
    Date of Patent: March 15, 2016
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Tai-Song Jin, Dong-Hoon Yoo, Bernhard Egger, Won-Sub Kim, Jin-Seok Lee, Sun-Hwa Kim, Hee-Jin Ahn
  • Patent number: 9262162
    Abstract: A register file is provided. The register file includes a plurality of registers configured to form at least one register cluster, each of the registers being configured to have a virtual index defined for each cluster and a physical index defined for each register, and an index converting unit configured to convert the virtual index to the physical index.
    Type: Grant
    Filed: August 9, 2011
    Date of Patent: February 16, 2016
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Bernhard Egger, Dong-Hoon Yoo, Won-Sub Kim
  • Patent number: 9164769
    Abstract: A reconfigurable array is provided. The reconfigurable array includes a Very Long Instruction Word (VLIW) mode and a Coarse-Grained Array (CGA) mode. When the VLIW mode is converted to the CGA mode, instead of sharing a central register file between the VLIW mode and the CGA mode, live data to be used in the CGA mode is copied from the central register file to local register files.
    Type: Grant
    Filed: December 8, 2010
    Date of Patent: October 20, 2015
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Won-Sub Kim, Tai-Song Jin, Dong-Hoon Yoo, Bernhard Egger, Jin-Seok Lee
  • Patent number: 9141498
    Abstract: A method for verifying an operation of a reconfigurable processor is provided. The method includes generating a random test program using a test description and an architecture description, executing the generated random test program in the reconfigurable processor and in a simulator, and then comparing types of output values in the execution result.
    Type: Grant
    Filed: September 6, 2013
    Date of Patent: September 22, 2015
    Assignees: SAMSUNG ELECTRONICS CO., LTD., SEOUL NATIONAL UNIVERSITY R&DB FOUNDATION
    Inventors: Seong-hoon Jeong, Bernhard Egger, Daeyong Shin, Changyeon Jo
  • Patent number: 9063735
    Abstract: Provided are a reconfigurable processor, which is capable of reducing the probability of an incorrect computation by analyzing the dependence between memory access instructions and allocating the memory access instructions between a plurality of processing elements (PEs) based on the results of the analysis, and a method of controlling the reconfigurable processor. The reconfigurable processor extracts an execution trace from simulation results, and analyzes the memory dependence between instructions included in different iterations based on parts of the execution trace of memory access instructions.
    Type: Grant
    Filed: October 13, 2011
    Date of Patent: June 23, 2015
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Hee-Jin Ahn, Dong-Hoon Yoo, Bernhard Egger, Min-Wook Ahn, Jin-Seok Lee, Tai-Song Jin, Won-Sub Kim