Patents by Inventor Bernhard Egger
Bernhard Egger has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 11954622Abstract: Provided are systems and methods for creating and managing an interactive process graphs which expedite performance of a multi-user enterprise process between user interfaces and the underlying systems. In one example, a method may include generating a process graph of a user interface process, wherein the process graph comprises nodes corresponding to activities and vertices between the nodes identifying dependencies among the activities, embedding input fields in the nodes of the process graph, embedding, via the process graph, an identifier of a current location of a data object within an instance within the user interface process, and displaying an instance of the process graph corresponding to the instance of the user interface process which includes the embedded input fields in the nodes and the identifier of the current location of the data object within the instance of the user interface process.Type: GrantFiled: January 18, 2022Date of Patent: April 9, 2024Assignee: SAP SEInventors: Gregor Berg, Andre Wenz, Sushovan Chattaraj, Lukas Egger, Bernhard Hoeppner
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Publication number: 20230195439Abstract: An apparatus includes a processor configured to generate each of intermediate representation codes corresponding to each of a plurality of loop structures obtained that corresponds to a neural network computation based on an input specification file of hardware; schedule instructions included in each of the intermediate representation codes corresponding to the plurality of loop structures; select, based on latency values predicted according to scheduling results of the intermediate representation codes, any one code among the intermediate representation codes; and allocate, based on a scheduling result of the selected intermediate representation code, instructions included in the selected intermediate representation code to resources of the hardware included in the apparatus.Type: ApplicationFiled: November 1, 2022Publication date: June 22, 2023Applicants: SAMSUNG ELECTRONICS CO., LTD., Seoul National University R&DB FoundationInventors: Bernhard EGGER, Hyemi MIN
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Patent number: 11301016Abstract: Provided are computing devices, each including a plurality of cores, and methods of allocating power to the plurality of cores. The computing device includes: a control core group including a plurality of control cores, the control core group configured to allocate a power budget to processing cores according to an energy management policy and state information of the processing cores, and transmit the allocated power budget to at least one of a lower control core and the processing cores; and a processing core group including at least one or more of the processing cores, the processing core group configured to perform computations based on the power budget allocated by the control core group, and transmit state information of the processing cores to the control core group, the state information of the processing cores having been modified based on the computations performed.Type: GrantFiled: July 22, 2019Date of Patent: April 12, 2022Assignees: SEOUL NATIONAL UNIVERSITY R&DB FOUNDATION, SAMSUNG ELECTRONICS CO., LTD.Inventors: Bernhard Egger, Younghyun Cho, Su-Rim Oh, Dong-hoon Yoo
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Publication number: 20210279587Abstract: A method and an apparatus for generating a code for a neural network operation are disclosed. The method includes receiving information on hardware configured to perform a neural network operation of the neural network, generating, using a processor, a target mapping model mapping the neural network operation on processing elements available to perform the neural network operation based on the information and a structure of the neural network, and generating a code to configure the hardware to perform the neural network operation based on the target mapping model.Type: ApplicationFiled: March 3, 2021Publication date: September 9, 2021Applicants: Samsung Electronics Co., Ltd., SNU R&DB FOUNDATIONInventors: Bernhard EGGER, Minsu KIM, Hyemi MIN
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Patent number: 10713095Abstract: A method of controlling a multi-core processor includes allocating at least one core of the multi-core processor to at least one process for execution; generating a translation table with respect to the at least one process to translate a logical ID of the at least one core allocated to the at least one process to a physical ID; and controlling the at least one process based on the translation table generated with respect to the at least one process.Type: GrantFiled: March 27, 2017Date of Patent: July 14, 2020Assignee: Samsung Electronics Co., Ltd.Inventors: Donghoon Yoo, Bernhard Egger
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Patent number: 10503557Abstract: A multi-core computing device includes a control core group having first low-level control cores and a processing core group. The control core group allocates work groups for executing an Open Computing Language (OpenCL) kernel to the first low-level control cores and first processing cores among the processing core group. The processing core group performs processing of the work groups allocated by the control core group outputs results of the processing. The control cores are hierarchically grouped.Type: GrantFiled: October 18, 2017Date of Patent: December 10, 2019Assignees: SAMSUNG ELECTRONICS CO., LTD., SEOUL NATIONAL UNIVERSITY R&DB FOUNDATIONInventors: Bernhard Egger, Su-Rim Oh, Younghyun Cho, Dong-Hoon Yoo
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Publication number: 20190339760Abstract: Provided are computing devices, each including a plurality of cores, and methods of allocating power to the plurality of cores. The computing device includes: a control core group including a plurality of control cores, the control core group configured to allocate a power budget to processing cores according to an energy management policy and state information of the processing cores, and transmit the allocated power budget to at least one of a lower control core and the processing cores; and a processing core group including at least one or more of the processing cores, the processing core group configured to perform computations based on the power budget allocated by the control core group, and transmit state information of the processing cores to the control core group, the state information of the processing cores having been modified based on the computations performed.Type: ApplicationFiled: July 22, 2019Publication date: November 7, 2019Applicants: Samsung Electronics Co., Ltd., SEOUL NATIONAL UNIVERSITY R&DB FOUNDATIONInventors: Bernhard Egger, Younghyun CHO, Su-Rim Oh, Dong-hoon Yoo
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Patent number: 10409351Abstract: Provided are computing devices, each including a plurality of cores, and methods of allocating power to the plurality of cores. The computing device includes: a control core group including a plurality of control cores, the control core group configured to allocate a power budget to processing cores according to an energy management policy and state information of the processing cores, and transmit the allocated power budget to at least one of a lower control core and the processing cores; and a processing core group including at least one or more of the processing cores, the processing core group configured to perform computations based on the power budget allocated by the control core group, and transmit state information of the processing cores to the control core group, the state information of the processing cores having been modified based on the computations performed.Type: GrantFiled: October 19, 2017Date of Patent: September 10, 2019Assignees: Samsung Electronics Co., Ltd., Seoul National University R&DB FoundationInventors: Bernhard Egger, Younghyun Cho, Su-Rim Oh, Dong-hoon Yoo
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Patent number: 10140247Abstract: Methods and apparatuses are provided for compressing configuration data. The configuration data, which includes control data corresponding to at least one processing unit used in each of a plurality of cycles, is stored. A plurality of processing units of a reconfigurable processor is divided into a plurality of groups. The configuration data is partitioned into a plurality of pieces of sub-configuration data. Each piece of sub-configuration data corresponding to a respective one of the plurality of groups. If a plurality of adjacent cycles include identical control data, the configuration data is compressed by deleting control data of all but one of the plurality of adjacent cycles, for each sub-configuration data.Type: GrantFiled: September 6, 2017Date of Patent: November 27, 2018Assignees: Samsung Electronics Co., Ltd, Seoul National University R&DB FoundationInventors: Bernhard Egger, Ho-chan Lee, Yeon-bok Lee, Suk-jin Kim
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Publication number: 20180246554Abstract: Provided are computing devices, each including a plurality of cores, and methods of allocating power to the plurality of cores. The computing device includes: a control core group including a plurality of control cores, the control core group configured to allocate a power budget to processing cores according to an energy management policy and state information of the processing cores, and transmit the allocated power budget to at least one of a lower control core and the processing cores; and a processing core group including at least one or more of the processing cores, the processing core group configured to perform computations based on the power budget allocated by the control core group, and transmit state information of the processing cores to the control core group, the state information of the processing cores having been modified based on the computations performed.Type: ApplicationFiled: October 19, 2017Publication date: August 30, 2018Applicants: Samsung Electronics Co., Ltd., Seoul National University R&DB FoundationInventors: Bernhard EGGER, Younghyun CHO, Su-Rim OH, Dong-hoon YOO
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Publication number: 20180181443Abstract: A multi-core computing device includes a control core group having first low-level control cores and a processing core group. The control core group allocates work groups for executing an Open Computing Language (OpenCL) kernel to the first low-level control cores and first processing cores among the processing core group. The processing core group performs processing of the work groups allocated by the control core group outputs results of the processing. The control cores are hierarchically grouped.Type: ApplicationFiled: October 18, 2017Publication date: June 28, 2018Applicant: SEOUL NATIONAL UNIVERSITY R&DB FOUNDATIONInventors: BERNHARD EGGER, Su-Rim Oh, Younghyun Cho, Dong-Hoon Yoo
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Patent number: 9959191Abstract: A dynamic library profiling method and a dynamic library profiling system including writing a first break point instruction at a start address of a dynamic library function, recording a first event count value that is a process performance management unit (PMU) count when a target process executes the first break point instruction, writing a second break point instruction to a return address of the dynamic library function, and calculating a PMU count generated in a processor core while the dynamic library function is executed, by comparing the recorded first event count value with a second event count value that is a process PMU count when the target process executes the second break point instruction, wherein the process PMU count is a cumulative value of PMU counts generated in the processor core while the target process is executed.Type: GrantFiled: November 22, 2013Date of Patent: May 1, 2018Assignees: SAMSUNG ELECTRONICS CO., LTD., SEOUL NATIONAL UNIVERSITY R&DB FOUNDATIONInventors: Min-Ju Lee, Bernhard Egger, Jae-jin Lee, Young-Lak Kim, Hong-Gyu Kim, Hong-June Kim
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Publication number: 20180067895Abstract: Methods and apparatuses are provided for compressing configuration data. The configuration data, which includes control data corresponding to at least one processing unit used in each of a plurality of cycles, is stored. A plurality of processing units of a reconfigurable processor is divided into a plurality of groups. The configuration data is partitioned into a plurality of pieces of sub-configuration data. Each piece of sub-configuration data corresponding to a respective one of the plurality of groups. If a plurality of adjacent cycles include identical control data, the configuration data is compressed by deleting control data of all but one of the plurality of adjacent cycles, for each sub-configuration data.Type: ApplicationFiled: September 6, 2017Publication date: March 8, 2018Inventors: Bernhard EGGER, Ho-chan LEE, Yeon-bok LEE, Suk-jin KIM
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Publication number: 20170277571Abstract: A method of controlling a multi-core processor includes allocating at least one core of the multi-core processor to at least one process for execution; generating a translation table with respect to the at least one process to translate a logical ID of the at least one core allocated to the at least one process to a physical ID; and controlling the at least one process based on the translation table generated with respect to the at least one process.Type: ApplicationFiled: March 27, 2017Publication date: September 28, 2017Applicants: Samsung Electronics Co., Ltd., Seoul National University R&DB FoundationInventors: Donghoon YOO, Bernhard EGGER
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Patent number: 9727528Abstract: Provided is a reconfigurable processor capable of reducing the routing processing time of routing nodes by driving the routing nodes at a greater frequency than a driving frequency of the processing elements. The reconfigurable processor includes one or more processing elements configured to be driven at a first driving frequency, and one or more routing nodes configured to be provided on paths that are formed between the processing elements, and to be driven at a second driving frequency that is greater than the first driving frequency.Type: GrantFiled: July 7, 2011Date of Patent: August 8, 2017Assignee: Samsung Electronics Co., Ltd.Inventors: Bernhard Egger, Taisong Jin, Won-Sub Kim
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Patent number: 9411582Abstract: An apparatus for processing an invalid operation in a prologue and/or an epilogue of a loop includes a register file including a first region for storing a data validity value indicating whether data is valid or invalid, and a second region for storing the data; and a functional unit configured to determine whether an operation is valid or invalid based on a value of a first region of each of one or more input sources received from the register file, and output a destination including a value based on the value of the first region of each of the input sources.Type: GrantFiled: March 15, 2013Date of Patent: August 9, 2016Assignees: Samsung Electronics Co., Ltd., Seoul Electronics University R&DB FoundationInventors: Seong-Hun Jeong, Bernhard Egger, Won-Sub Kim
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Patent number: 9342480Abstract: An apparatus and method for generating a very long instruction word (VLIW) command that supports predicated execution, and a VLIW processor and method for processing a VLIW are provided herein. The VLIW command includes an instruction bundle formed of a plurality of instructions to be executed in parallel and a single value indicating predicated execution, and is generated using the apparatus and method for generating a VLIW command. The VLIW processor decodes the instruction bundle and executes the instructions, which are included in the decoded instruction bundle, in parallel, according to the value indicating predicated execution.Type: GrantFiled: October 28, 2013Date of Patent: May 17, 2016Assignee: Samsung Electronics Co., Ltd.Inventors: Bernhard Egger, Soo-jung Ryu, Dong-hoon Yoo, Il-hyun Park
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Patent number: 9304967Abstract: Provided is a reconfigurable processor that may process a first type of operation in first mode using a first group of functional units, and process a second type of operation in second mode using a second group of functional units. The reconfigurable processor may selectively supply power to either the first group or the second group, in response to a mode-switch signal or a mode-switch instruction.Type: GrantFiled: August 19, 2011Date of Patent: April 5, 2016Assignees: Samsung Electronics Co., Ltd., POSTECH ACADEMY-INDUSTRY FOUNDATIONInventors: Sung-Joo Yoo, Yeon-Gon Cho, Bernhard Egger, Won-Sub Kim, Hee-Jin Ahn
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Patent number: 9286074Abstract: An instruction compressing apparatus and method for a parallel processing computer such as a very long instruction word (VLIW) computer, are provided. The instruction compressing apparatus includes a bundle code generating unit, an instruction compressing unit, and an instruction converting unit. The bundle code generating unit may generate a bundle code in response to an input of instructions to be compressed. The bundle code may indicate whether a current instruction group is terminated, and also whether an instruction group following the current instruction group is a no-operation (NOP) instruction group. The instruction compressing unit may remove a NOP instruction and/or a NOP instruction group from the input instructions according to the generated bundle code. The instruction converting unit may include the generated bundle code in the remaining instructions which have not been removed by the instruction compressing unit.Type: GrantFiled: October 26, 2010Date of Patent: March 15, 2016Assignee: Samsung Electronics Co., Ltd.Inventors: Tai-Song Jin, Dong-Hoon Yoo, Bernhard Egger, Won-Sub Kim, Jin-Seok Lee, Sun-Hwa Kim, Hee-Jin Ahn
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Patent number: 9262162Abstract: A register file is provided. The register file includes a plurality of registers configured to form at least one register cluster, each of the registers being configured to have a virtual index defined for each cluster and a physical index defined for each register, and an index converting unit configured to convert the virtual index to the physical index.Type: GrantFiled: August 9, 2011Date of Patent: February 16, 2016Assignee: Samsung Electronics Co., Ltd.Inventors: Bernhard Egger, Dong-Hoon Yoo, Won-Sub Kim