Abstract: We disclose herein a method of compressing data for data transfer within an electronic device. The method comprises: receiving, at a first processing member of the electronic device, a plurality of data samples produced by a member of the electronic device, wherein the data samples comprise numerical bits; restructuring, by the first processing member, the plurality of data samples into a plurality of data packets; labelling each data packet with a sample indicator bit to indicate a plurality of groups across the plurality of data packets; transferring a bit stream comprising at least some of the plurality of data packets across an interface of the electronic device to a receiving member of the electronic device; and decoding the bit stream, by a second processing member of the electronic device, to obtain at least some of the plurality of the data samples, the decoding being based at least in part on the sample indicator bits.

Abstract: An optical sensor arrangement comprises a photodiode (11), an integrator (12) with an integrator input (15) coupled to the photodiode (11), a comparator (13) with a first input (18) coupled to an integrator output (16) of the integrator (12), and a reference capacitor circuit (14) that is coupled to the integrator input (15) and is designed to provide a charge package to the integrator input (15). In a start phase (A), charge packages are provided to the integrator input (15), until a comparator input voltage (VIN) at the first input (18) of the comparator (13) crosses a comparator switching point.

Abstract: A method is suggested for sensing light being incident on an electronic device. The electronic device comprises a display and a light sensor arrangement mounted behind the display such as to receive incident light through the display. The method comprises periodically switching the display on and off depending on a control signal, wherein a period is defined by a succession of an on-state and an off-state of the display. A sensor signal is generated by integrating the incident light by means of the light sensor arrangement for a total integration time comprising a number of periods. A first signal count is determined from the sensor signal being indicative of an amount of integrated incident light during an on-state. A second signal count is determined from the sensor signal being indicative of an amount of integrated incident light during an off-state. A third signal count is determined from the sensor signal being indicative of an amount of integrated incident light during the total integration time.

Abstract: A method is suggested for sensing light being incident on an electronic device. The electronic device comprises a display and a light sensor arrangement mounted behind the display such as to receive incident light through the display. The method comprises periodically switching the display on and off depending on a control signal, wherein a period is defined by a succession of an on-state and an off-state of the display. A sensor signal is generated by integrating the incident light by means of the light sensor arrangement for a total integration time comprising a number of periods. A first signal count is determined from the sensor signal being indicative of an amount of integrated incident light during an on-state. A second signal count is determined from the sensor signal being indicative of an amount of integrated incident light during an off-state. A third signal count is determined from the sensor signal being indicative of an amount of integrated incident light during the total integration time.

Abstract: An optical sensor arrangement comprises a photodiode (11), an integrator (12) with an integrator input (15) coupled to the photodiode (11), a comparator (13) with a first input (18) coupled to an integrator output (16) of the integrator (12), and a reference capacitor circuit (14) that is coupled to the integrator input (15) and is designed to provide a charge package to the integrator input (15). In a start phase (A), charge packages are provided to the integrator input (15), until a comparator input voltage (VIN) at the first input (18) of the comparator (13) crosses a comparator switching point.

Abstract: An optical proximity sensor arrangement comprises a first sensor unit with a first emitter and a first detector and a second sensor unit with a second emitter and/or a second detector. The first detector is configured to detect light being emitted by the first emitter and, if applicable, by the second emitter, and being at least partially reflected. If applicable, the second detector is configured to detect light being emitted by the first emitter and being at least partially reflected. A distance between the first emitter and the first detector is, if applicable, less than a distance between the first detector and the second emitter and, if applicable, less than a distance between the first emitter and the second detector.

Abstract: A receiver circuit for receiving an input signal (IDD, UDD) comprises a detector circuit (111, 111a, 111b, 111c, 111d, 111e, 111f), which is in the form of a sample-and-hold circuit for determining a reference level of the input signal or in the form of a filter circuit for generating a mean value of levels of the input signal (IDD, UDD). The detector circuit generates, on the output side, a referential signal (RS), which is supplied to comparator circuits (113a, 113b, 113c, 113d, 115a, 115b, 115c, 115d). The comparator circuits (113a, 113b, 113c, 113d, 115a, 115b, 115c, 115d) compare an offset level of the input signal (IDD, UDD) with the referential signal (RS) and generate data signals (DATA, DH, DL). The offset input signals (IDD, UDD) are evaluated relatively in respect of the reference level or the mean value of the levels of the input signal.

Abstract: A receiver circuit for receiving an input signal (IDD, UDD) comprises a detector circuit (111, 111a, 111b, 111c, 111d, 111e, 111f), which is in the form of a sample-and-hold circuit for determining a reference level of the input signal or in the form of a filter circuit for generating a mean value of levels of the input signal (IDD, UDD). The detector circuit generates, on the output side, a referential signal (RS), which is supplied to comparator circuits (113a, 113b, 113c, 113d, 115a, 115b, 115c, 115d). The comparator circuits (113a, 113b, 113c, 113d, 115a, 115b, 115c, 115d) compare an offset level of the input signal (IDD, UDD) with the referential signal (RS) and generate data signals (DATA, DH, DL). The offset input signals (IDD, UDD) are evaluated relatively in respect of the reference level or the mean value of the levels of the input signal.

Abstract: An amplification arrangement comprises a signal-processing element (SVE) with an integrator element (INT) that is coupled on the input side with a first input (E1) for feeding the input signal and with a second input (E2) for feeding a feedback signal. The signal-processing element (SVE) is designed to set a respective level of the input signal and/or the feedback signal as a function of a control signal. The amplifier arrangement furthermore comprises a pulse modulator (PM) that is designed to generate a pulse signal on a pulse output (POT) as a function of a signal applied on the output (SOT) of the signal-processing element (SVE). An output stage (OST) comprises a switching element (SW) that is designed to connect supply-voltage terminals (V1, V2, GND) to an output terminal (OOT) that is coupled with an amplifier output (AOT) and the second input (E2), and a control unit (CU) for driving the switching element (SW) that is coupled with the pulse output (POT).

Abstract: An input circuit arrangement comprises an input, a comparator, and an evaluation circuit. The input is designed for coupling to a first terminal of an impedance and for feeding an input signal. The comparator is connected to the input of the input circuit arrangement and is designed for delivering an activation signal to an output as a function of a comparison of the input signal with an adjustable threshold. Furthermore, the evaluation circuit is connected to the input of the input circuit arrangement and for its activation to the output of the comparator and is designed for evaluating the value of the impedance that can be connected.

Abstract: An amplification arrangement comprises a signal-processing element (SVE) with an integrator element (INT) that is coupled on the input side with a first input (E1) for feeding the input signal and with a second input (E2) for feeding a feedback signal. The signal-processing element (SVE) is designed to set a respective level of the input signal and/or the feedback signal as a function of a control signal. The amplifier arrangement furthermore comprises a pulse modulator (PM) that is designed to generate a pulse signal on a pulse output (POT) as a function of a signal applied on the output (SOT) of the signal-processing element (SVE). An output stage (OST) comprises a switching element (SW) that is designed to connect supply-voltage terminals (V1, V2, GND) to an output terminal (OOT) that is coupled with an amplifier output (AOT) and the second input (E2), and a control unit (CU) for driving the switching element (SW) that is coupled with the pulse output (POT).

Abstract: An input circuit arrangement (1) comprises an input (2), a comparator (30), and an evaluation circuit (50). The input (2) is designed for coupling to a first terminal (101) of an impedance (100) and for feeding an input signal (ES). The comparator (30) is connected to the input (2) of the input circuit arrangement (1) and is designed for delivering an activation signal (S1) to an output (31) as a function of a comparison of the input signal (ES) with an adjustable threshold (SW1). Furthermore, the evaluation circuit (50) is connected to the input (2) of the input circuit arrangement (1) and for its activation to the output (31) of the comparator (30) and is designed for evaluating the value of the impedance (100) that can be connected.