Abstract: A structure is designed with an external terminal (100) and a reference terminal (130). A first transistor (106) has a current path coupled to the external terminal and has a first control terminal (114). A second transistor (110) has a current path coupled between the current path of the first transistor and the reference terminal and has a second control terminal (126). A bias circuit comprises a third transistor (116) having a first conductivity type and a fourth transistor (124) having a second conductivity type. The third and fourth transistors have respective current paths coupled in series to the reference terminal. The bias circuit is arranged to produce a first voltage at the first control terminal and a second voltage different from the first voltage at the second control terminal.

Abstract: An integrated circuit is provided with a local electrostatic discharge (ESD) protection circuitry (120) associated with each signal pad. The integrated circuit has internal circuitry (100) that operates at a low supply voltage, but at least some of the interface signals impressed on the signal pads operate at a high supply voltage. The local ESD protection circuitry associated with each signal pad comprises only a pair of diodes connected respectively to the ground reference bus and a high voltage supply bus. A few shared clamp circuits (222) are connected to the voltage buses and clamp any ESD voltage surge that is transferred to the high voltage bus by the individual signal pad ESD protection circuits. The clamp circuits use cascoded low voltage MOS devices (P1, N1, P2) that are biased during normal operation so that electrical over-stress does not occur.

Abstract: A voltage level shifter with testable cascode devices is disclosed. According to one embodiment, the level shifter includes multiple cascode devices and switches a first output driver according to the values of a data input and an enable input. Testability devices coupled to cascode devices of the level shifter detect a current in response to failure of the corresponding cascode device.

Abstract: A clock multiplier (40) comprises a digital phase lock loop circuit having a single variable delay stage (44) for generating high and low phases for the output clocks. The variable delay stage (44) includes a commutator 64 which chooses between the signal propagating on first and second delay paths (52 and 54). The delay on the delay paths can be incrementally adjusted using capacitors (58 and 61) selectively enabled between the path and ground. If the variable delay is insufficient to lock the output to the reference clock, a prescaler (72) automatically divides the output as needed. A stutter mode prevents short pulses, caused by a transition of the reference clock arriving shortly after the transition of the output clock to a low state, from being passed to the clock multiplying circuitry. The clock multiplier (40) may use a free running mode after lock is obtained, where adjustments are made relative to the degree of difference between the output clock and the reference clock.

Abstract: A clock multiplier (40) comprises a digital phase lock loop circuit having a single variable delay stage (44) for generating high and low phases for the output clocks. The variable delay stage (44) includes a commutator 64 which chooses between the signal propagating on first and second delay paths (52 and 54). The delay on the delay paths can be incrementally adjusted using capacitors (58 and 61) selectively enabled between the path and ground. If the variable delay is insufficient to lock the output to the reference clock, a prescaler (72) automatically divides the output as needed. A stutter mode prevents short pulses, caused by a transition of the reference clock arriving shortly after the transition of the output clock to a low state, from being passed to the clock multiplying circuitry. The clock multiplier (40) may use a free running mode after lock is obtained, where adjustments are made relative to the degree of difference between the output clock and the reference clock.

Abstract: An integrated circuit is provided with a local electrostatic discharge (ESD) protection circuitry (120) associated with each signal pad. The integrated circuit has internal circuitry (100) that operates at a low supply voltage, but at least some of the interface signals impressed on the signal pads operate at a high supply voltage. The local ESD protection circuitry associated with each signal pad comprises only a pair of diodes connected respectively to the ground reference bus and a high voltage supply bus. A few shared clamp circuits (222) are connected to the voltage buses and clamp any ESD voltage surge that is transferred to the high voltage bus by the individual signal pad ESD protection circuits. The clamp circuits use cascoded low voltage MOS devices (P1, N1, P2) that are biased during normal operation so that electrical over-stress does not occur.

Abstract: An integrated circuit is provided with a local electrostatic discharge (ESD) protection circuitry (120) associated with each signal pad. The integrated circuit has internal circuitry (100) that operates at a low supply voltage, but at least some of the interface signals impressed on the signal pads operate at a high supply voltage. The local ESD protection circuitry associated with each signal pad comprises only a pair of diodes connected respectively to the ground reference bus and a high voltage supply bus. A few shared clamp circuits (222) are connected to the voltage buses and clamp any ESD voltage surge that is transferred to the high voltage bus by the individual signal pad ESD protection circuits. The clamp circuits use cascoded low voltage MOS devices (P1, N1, P2) that are biased during normal operation so that electrical over-stress does not occur.

Abstract: An integrated circuit is provided with electrostatic discharge (ESD) protection circuitry (120) which uses low voltage transistors (N1, N2) to provide protection to a signal pad that handles high voltage signals during normal operation of the integrated circuit. The external signal is operable at a second supply voltage that is higher than the Vdd supply voltage. The internal circuitry of the integrated circuit is comprised of MOS transistors that have gate oxide of a first thickness that has a Vox-max suitable for the Vdd supply voltage but not for the second supply voltage. The ESD protection transistors use the same gate oxide thickness as the MOS transistors used in the internal circuitry. A substrate region in the semiconductor substrate is enclosed by a highly doped region (250) so that the back-gates of the ESD protection transistors can be voltage pumped by pump circuitry (202) in order to trigger bipolar conduction of the ESD protection transistors at a lower voltage.

Abstract: A fail-safe Input/Output buffer bias circuit for digital CMOS chips provides protection for Input/Output buffers which have high voltages applied to the Input/output node and are subjected to power supply failure resulting in a collapsing supply voltage decaying to zero volts while said Input/output circuit has a high voltage remaining applied to its Input/output node. The Input/output buffer bias circuit is comprised of a sensing circuit and a bias generator circuit which acts to drive protection transistors in a manner which optimally minimizes the voltage impressed on input or output devices under all conditions which could persist in the event of VDD supply voltage failure. Protection circuitry holds all three combinations of voltage stress, gate-to-source, gate-to-drain, and drain-to-source voltages, to acceptable levels.

Abstract: A test circuit (10) is provided to enable testing for faults in internal cascode transistors Q2 and Q3, which form part of, for example, a level shifting circuit. Test circuit (10) is comprised of test transistors Q6 and Q7 connected to regulating transistors Q5 and Q8. When Q2 and Q3 are functioning properly, no current flow through test circuit (10). If, however, either or both of Q2 or Q3 has a drain to source short, current flows through test circuit (10) thus providing an indication of the fault.

Abstract: An integrated circuit is provided with electrostatic discharge (ESD) protection circuitry (120) A substrate region in the semiconductor substrate is enclosed by a ring of highly doped region (350). An NMOS ESD protection transistor (N1) with its backgate in the enclosed substrate region can be voltage pumped by pump circuitry (N2) in order to trigger bipolar conduction of the ESD protection transistor at a lower voltage. Control circuitry (304) is connected to the signal bond pad and to the gate of amplifier circuitry (P1) to provide a voltage pulse in response to an ESD zap applied to the signal bond pad. PMOS amplifier circuitry (P1) provides an amplified voltage pulse to the pump circuitry with a magnitude approximately equal to the ESD potential on the signal pad so that a strong pump current is provided to the highly doped ring.

Abstract: A clock multiplier (40) comprises a digital phase lock loop circuit having a single variable delay stage (44) for generating high and low phases for the output clocks. The variable delay stage (44) includes a commutator 64 which chooses between the signal propagating on first and second delay paths (52 and 54). The delay on the delay paths can be incrementally adjusted using capacitors (58 and 61) selectively enabled between the path and ground. If the variable delay is insufficient to lock the output to the reference clock, a prescaler (72) automatically divides the output as needed. A stutter mode prevents short pulses, caused by a transition of the reference clock arriving shortly after the transition of the output clock to a low state, from being passed to the clock multiplying circuitry. The clock multiplier (40) may use a free running mode after lock is obtained, where adjustments are made relative to the degree of difference between the output clock and the reference clock.

Abstract: A method and circuit for detecting a spurious lock signal from a lock detect circuit are disclosed. The method includes generating a lock signal (16, 58, 84) having two states: lock and unlock. The lock signal (16, 58, 84) is monitored at a debounce circuit (50, 80). A reference clock signal (56, 86) is then received at the debounce circuit (50, 80). A clean lock signal (68, 88) is generated by the debounce circuit (50, 80) when the lock state of the lock signal (16, 58, 84) is received for at least two cycles of the reference clock. If the lock state of the lock signal (16, 58, 84) is received for less than two cycles of the reference clock, a clean loss-of-lock signal (68, 88) is generated. The circuit for detecting a spurious lock signal (50, 80) includes a lock detect circuit for generating a lock signal (10) and a plurality of flip-flops (70, 72, 92, 94, 96, 98).

Abstract: A protection device for trench isolated technologies. The protection device includes a lateral SCR (100) that incorporates a triggering MOS transistor (120) with a first gate electrode (116) connected to the cathode (112) of the SCR (100). The anode (110) of the lateral SCR (100) is separated from the nearest source/drain region (122) of the triggering MOS transistor (120) by a second gate electrode (132) rather than by trench isolation. By using the second gate electrode (132) for isolation instead of trench isolation, the surface conduction of the lateral SCR (100) in unimpeded.

Abstract: According to one embodiment of the present invention, an output buffer (200) includes a first output driver (86) having a gate oxide protected from voltage changes on an output (16). A second output driver (88) also has a gate oxide protected from voltage changes on the output (16). A level shifter (60) includes at least one cascode device (66, 68, 70, 72) and switches the first output driver (86) according to the values of a data input (12) and an enable input (14). A bias-generation circuit (300) generates a quasi-failsafe voltage that is approximately equal to a chip core voltage when a power supply (4) is supplying the chip core voltage and equal to a portion of the chip core voltage when the power supply (4) is not supplying the chip core voltage. The bias-generation circuit (300) is coupled to a first output cascode (80) coupled to the first output driver (86), to a second output cascode (84) coupled to the second output driver (88), or to the cascode device (66, 68, 70, 72) of the level shifter (60).

Abstract: According to one embodiment of the present invention, an output buffer (200) includes a first output driver (86) and a second output driver (88). A first output cascode (80) coupled to the first output driver (86) protects the gate oxide of the first output driver (86) from voltage changes on the output (16). A second output cascode (84) coupled to the second output driver (88) protects the gate oxide of the second output driver (88) from voltage changes on the output (16). A level shifter (60) includes multiple cascode devices (66, 68, 70, 72) and switches the first output driver according to the values of a data input (12) and an enable input (14). A first testability device (202, 204, 206, 208) coupled to a cascode device (66, 68, 70, 72) of the level shifter (60) generates a current in response to failure of the cascode device (66, 68, 70, 72).

Abstract: A clock multiplier (40) comprises a digital phase lock loop circuit having a single variable delay stage (44) for generating high and low phases for the output clocks. The variable delay stage (44) includes a commutator 64 which chooses between the signal propagating on first and second delay paths (52 and 54). The delay on the delay paths can be incrementally adjusted using capacitors (58 and 61) selectively enabled between the path and ground. If the variable delay is insufficient to lock the output to the reference clock, a prescaler (72) automatically divides the output as needed. A stutter mode prevents short pulses, caused by a transition of the reference clock arriving shortly after the transition of the output clock to a low state, from being passed to the clock multiplying circuitry. The clock multiplier (40) may use a free running mode after lock is obtained, where adjustments are made relative to the degree of difference between the output clock and the reference clock.

Abstract: A device and method for reducing phase jitter in digital phase locked loop applications resulting in smaller clock skews between application specific integrated circuits (ASICs). Phase jitter is reduced by a fine resolution digital delay line (20) comprising both coarse stages (variable delay element 24) for rough/fast phase adjustment and fine stages (fine resolution delay element 22) for precise delay adjustment when phase lock is near.

Abstract: An output buffer with a slew rate that is load independent is comprised of an output buffer (14) that is connected to an output terminal (12). The output buffer (14) is controlled such that it can drive a load (18) with different drive levels by changing the transconductance internal thereto. The transition on the input to the buffer (14) is passed through an intrinsic delay block (34) and variable delay block (40) to provide a delay signal on a node (42). A first phase detector latch (50) with a first threshold voltage compares this transition with the transition on the output terminal (12). A second phase detector latch (60) with a second threshold voltage, also compares this delayed transition with that on the output terminal (12). If both of the latches (50) and (60) indicate that the delayed transition occurred after the transition on the output terminal (12), a control signal on a line (78) is changed by incrementing a counter (74). This will increase the drive to a load (18).

Abstract: A device and method for reducing phase jitter in digital phase locked loop applications resulting in smaller clock skews between application specific integrated circuits (ASICs). Phase jitter is reduced by a fine resolution digital delay line (20) comprising both coarse stages (variable delay element 24) for rough/fast phase adjustment and fine stages (fine resolution delay element 22) for precise delay adjustment when phase lock is near.