Abstract: A data memory circuit is provided. In one embodiment, the data memory circuit comprises a plurality of addressable memory cells, a command decoding device for decoding external commands and a control device for controlling or initiating operations for the operation of the data memory circuit in each case in a manner dependent on the decoded commands. The memory circuit has critical operating states in which the execution of specific commands is impermissible resulting in the course of specific operations in the data memory circuit, wherein a command buffer device buffer-stores commands received during the duration of their impermissibility and releases them for execution after the end of their impermissibility.

Abstract: A DLL circuit for phase matching of a periodic input signal, having a variable delay unit, having a delay element and having a regulation unit which has a regulation device, for setting an input signal delay in the delay unit, and a comparator unit, in order to generate a phase signal in each signal cycle, the state of which phase signal indicates that the input signal is leading or lagging a signal which has been delayed by the variable delay unit and the delay element, and which is provided to the regulation device during a steady-state operating phase, with the regulation device increasing the delay of the delay unit during an initial transient phase until a change in the phase signal indicates a change from identified lagging of the input signal to leading of the input signal, wherein the regulation unit has a filter circuit in order to provide a filtered phase signal to the regulation device during the initial transient phase, with the filter circuit changing the state of the filtered phase signal to the

Abstract: A semiconductor memory has a data signal path and a control device in order to supply functional elements of the data signal path with control signals. Programmable delays are connected into the signal lines providing the control signals, so that the time relationships between the control signals can be set reversibly via a soft set register or irreversibly via fuses. This enables simple adaptation of the internal control signal timing to fluctuations in the fabrication process or after conversion of the configuration to a new fabrication process.