Abstract: The invention relates to a method for determining processing image induced defects in the manufacture of semiconductor products such as wafers by analyzing the circuit design of the product mask and modifying a conventional test defect structure to mimic the product mask to incorporate one or more isolated or other features including product mask circuit features likely to cause processing image induced defects into the test defect structure.

Abstract: A method and apparatus are provided for improving the leveling and, consequently, the focusing of a substrate such as a wafer during the photolithography imaging procedure of a semiconductor manufacturing process. The invention performs a pre-scan of the wafer's topography and assigns importance values to different regions of the wafer surface. Exposure focus instructions are calculated based on the topography and importance values of the different regions and the wafer is then scanned and imaged based on the calculated exposure focus instructions.

Abstract: A lithographic process including providing a first wafer including (i) a first substrate, (ii) a first underlying layer on the first substrate, and (iii) a first resist layer on the first underlying layer; exposing a first plurality of full exposure fields of a first top resist layer plane through a product reticle, wherein the first top resist layer plane comprises a first top resist layer surface of the first resist layer, and wherein each full exposure field of the first plurality of full exposure fields is completely within the first top resist layer surface; and exposing a first plurality of partial exposure fields of the first top resist layer plane through a dummy reticle different from the product reticle, wherein each partial exposure field of the first plurality of partial exposure fields is partially but not totally within the first top resist layer surface.

Abstract: Corner rounding and image shortening is substantially reduced in an image printed on a substrate by illuminating a photolithographic mask and projecting light transmitted through the photolithographic mask onto the substrate using an optical projection system. The photolithographic mask has a mask pattern that includes at least one printable feature having at least one corner. Incorporated, in the mask pattern, is at least one line feature corresponding to the corner of the printable feature. The line feature is in at least close proximity to the corresponding corner of the printable feature and has a line width that is smaller than a minimum resolution of the optical projection system.

Abstract: There is provided a method for aligning a semiconductor wafer and a mask. A semiconductor wafer is provided having an alignment mark formed thereon. A mask is provided having a pattern formed thereon. The mask is illuminated so as to create a bright spot thereon by a 0_&pgr; phase conflict. The alignment mark is aligned with the bright spot, so as to align the semiconductor wafer with the mask. Preferably, the method includes the step of creating the alignment mark on the semiconductor wafer in a form of a frame. Moreover, preferably, the creating step includes the step of creating the frame to minimize an impact of film stack variations.

Abstract: A method for intra-cell alignment of a substrate and mask comprises providing a substrate comprising an exposed photosensitive material, providing a phase-shift mask, and aligning the phase-shift mask to an intra-cell structure on the substrate.

Abstract: A method of transferring a pattern onto a substrate during IC fabrication is disclosed. The substrate is coated with a photosensitive layer having compounds dissolved in a solvent. Roughness on the sidewalls of the photosensitive layer is eliminated or reduced by evaporating the solvent without using elevated temperatures.

Abstract: A method for intra-cell alignment of a substrate and mask comprises providing a substrate comprising an exposed photosensitive material, providing a phase-shift mask, and aligning the phase-shift mask to an intra-cell structure on the substrate.

Abstract: Corner rounding and image shortening is substantially reduced in an image printed on a substrate by illuminating a photolithographic mask and projecting light transmitted through the photolithographic mask onto the substrate using an optical projection system. The photolithographic mask has a mask pattern that includes at least one printable feature having at least one corner. Incorporated, in the mask pattern, is at least one line feature corresponding to the corner of the printable feature. The line feature is in at least close proximity to the corresponding corner of the printable feature and has a line width that is smaller than a minimum resolution of the optical projection system.

Abstract: Disclosed is a method of aligning a mask with a semiconductor wafer surface, comprising the steps of providing a semiconductor surface with one or more wafer alignment marks thereon, providing a mask with one or more etchings effective in generating one or more 0-&pgr;-phase-conflict alignment marks under ambient lighting conditions of use, wherein each said wafer alignment mark is of a geometry that is compatibly aligning with a corresponding 0-&pgr;-phase-conflict alignment mark, and aligning said 0-&pgr;-phase-conflict alignment marks with their corresponding wafer alignment marks.

Abstract: There is provided a method for aligning a semiconductor wafer and a mask. A semiconductor wafer is provided having an alignment mark formed thereon. A mask is provided having a pattern formed thereon. The mask is illuminated so as to create a bright spot thereon by a 0_&pgr; phase conflict. The alignment mark is aligned with the bright spot, so as to align the semiconductor wafer with the mask. Preferably, the method includes the step of creating the alignment mark on the semiconductor wafer in a form of a frame. Moreover, preferably, the creating step includes the step of creating the frame to minimize an impact of film stack variations.