Abstract: A carrier having one or more conductive terminals is provided. A semiconductor die is mounted on the carrier. The semiconductor die is electrically connected to the one or more conductive terminals. The semiconductor die is encapsulated with an electrically insulating mold compound. A verification rule that tests whether inputted information satisfies authentication criteria is created. A first identification feature is formed on a metal structure that is encapsulated by the mold compound. The first identification feature comprises one or more symbols from a first data representation scheme that are covered by the mold compound. The one or more symbols of the first identification feature are selected to convey information that satisfies the authentication criteria of the verification rule.

Abstract: A carrier having one or more conductive terminals is provided. A semiconductor die is mounted on the carrier. The semiconductor die is electrically connected to the one or more conductive terminals. The semiconductor die is encapsulated with an electrically insulating mold compound. A verification rule that tests whether inputted information satisfies authentication criteria is created. A first identification feature is formed on a metal structure that is encapsulated by the mold compound. The first identification feature comprises one or more symbols from a first data representation scheme that are covered by the mold compound. The one or more symbols of the first identification feature are selected to convey information that satisfies the authentication criteria of the verification rule.

Abstract: According to one embodiment, a chip is described comprising a plurality of supply lines delimiting a plurality of cell areas and a gate comprising a first transistor and a second transistor, wherein the first transistor is located in a first cell area of the plurality of cell areas and the second transistor is located in a second cell area of the plurality of cell areas such that a supply line of the plurality of supply lines lies between the first cell area and the second cell area.

Abstract: According to one embodiment, a chip is described comprising a plurality of supply lines delimiting a plurality of cell areas and a gate comprising a first transistor and a second transistor, wherein the first transistor is located in a first cell area of the plurality of cell areas and the second transistor is located in a second cell area of the plurality of cell areas such that a supply line of the plurality of supply lines lies between the first cell area and the second cell area.

Abstract: Systems and methods for integrated circuit planar netlist interpretation are disclosed. In one embodiment, higher abstraction level descriptions of an integrated circuit are generated from a planar netlist and layout data of the integrated circuit. Various embodiments may derive the higher abstraction levels through, for example, netlist compression and netlist partitioning. Other embodiments may derive the higher abstraction levels using, for example, device and module hypothesis search functions based on device properties and design constraints derived from netlist and layout data.

Abstract: A data storing apparatus that wirelessly transmits data, wherein the apparatus is deformable so as to block wireless transmission of data when the apparatus is in the deformed state.

Abstract: A device for processing a program code with a plurality of subprogram calls, a subprogram corresponding to a subprogram call taking place by means of an allocation table, has a security module having the allocation table and a processor for using the program code. Access to the allocation table in the security module is restricted. The processor for using the program code is formed to retrieve, responsive to a request for subprogram data, using authorization information, subprogram data via the allocation table in the security module.

Abstract: Systems and methods for integrated circuit planar netlist interpretation are disclosed. In one embodiment, higher abstraction level descriptions of an integrated circuit are generated from a planar netlist and layout data of the integrated circuit. Various embodiments may derive the higher abstraction levels through, for example, netlist compression and netlist partitioning. Other embodiments may derive the higher abstraction levels using, for example, device and module hypothesis search functions based on device properties and design constraints derived from netlist and layout data.

Abstract: A data storing apparatus that wirelessly transmits data, wherein the apparatus is deformable so as to block wireless transmission of data when the apparatus is in the deformed state.

Abstract: An ohmic resistance is present between two parts of a conductor layer so that the size of the ohmic resistance can be ascertained and/or a semiconductor region is present in or on a layer forming the dielectric. The conductor layer is structured into a gate contact, a source contact, and a drain contact so that a transistor function or switching function is possible in the semiconductor region. Such a configuration allows an attempt to analyze the circuit integrated in the chip to be detected.

Abstract: A device for processing a program code with a plurality of subprogram calls, a subprogram corresponding to a subprogram call taking place by means of an allocation table, has a security module having the allocation table and a processor for using the program code. Access to the allocation table in the security module is restricted. The processor for using the program code is formed to retrieve, responsive to a request for subprogram data, using authorization information, subprogram data via the allocation table in the security module.

Abstract: An ohmic resistance is present between two parts of a conductor layer so that the size of the ohmic resistance can be ascertained and/or a semiconductor region is present in or on a layer forming the dielectric. The conductor layer is structured into a gate contact, a source contact, and a drain contact so that a transistor function or switching function is possible in the semiconductor region. Such a configuration allows an attempt to analyze the circuit integrated in the chip to be detected.