Abstract: A method of determining filter coefficients of an equalizer circuit for equalizing a non-linear electronic system is described. The equalizer circuit includes a Volterra filter circuit. Further, an equalizer circuit for equalizing a non-linear electronic system and an electronic device are described.

Abstract: The present disclosure relates to a parallel filter structure for processing a signal. The parallel filter structure includes a signal input configured to receive a time and value discrete input signal. The parallel filter structure includes a feed forward equalizer circuit connected with the signal input for receiving the time and value discrete input signal. The parallel filter structure includes a decision feedback equalizer circuit connected with the signal input for receiving the time and value discrete input signal. The feed forward equalizer circuit and the decision feedback equalizer circuit together form a parallel circuit. Further, an oscilloscope and a method of processing a signal are provided.

Abstract: A digital filter circuit is described. The digital filter circuit includes a digital filter input, at least two finite impulse response (FIR) filter circuits, and a connection circuit. The digital filter input is configured to receive a digital input signal set having a data parallelism. The at least two FIR filter circuits are configured to process the digital input signal set at least partially. The at least two FIR filter circuits include a pre-adder sub-circuit, a convolution sub-circuit, and a post-adder sub-circuit, respectively. The connection circuit is configured to selectively connect the at least two FIR filter circuits based on the data parallelism of the digital input signal set.

Abstract: A digital filter circuit is described. The digital filter circuit includes at least one signal input and at least one finite impulse response (FIR) filter associated with the at least one signal input. The at least one signal input is configured to receive an input signal, wherein the input signal includes a product of at least two input signal samples. The at least one FIR filter is established as a short-length FIR filter. Further, a signal processing method is described.

Abstract: A digital filter circuit for filtering at least two input signals having different signal data rates is described. The digital filter circuit includes an input multiplexer sub-circuit, a digital filter, and an output multiplexer sub-circuit. The digital filter is connected to the input multiplexer sub-circuit downstream of the input multiplexer sub-circuit. The digital filter is connected to the output multiplexer sub-circuit upstream of the output multiplexer sub-circuit. The input multiplexer sub-circuit is configured to receive the at least two input signals having different signal data rates. The input multiplexer sub-circuit is configured to selectively forward the at least two input signals to the digital filter. The digital filter is configured to filter the at least two input signals, thereby obtaining at least two filtered input signals. The output multiplexer sub-circuit is configured to selectively output the at least two filtered input signals.

Abstract: A digital filter circuit is described. The digital filter circuit includes at least one signal input and at least one finite impulse response (FIR) filter associated with the at least one signal input. The at least one signal input is configured to receive an input signal, wherein the input signal includes a product of at least two input signal samples. The at least one FIR filter is established as a short-length FIR filter. Further, a signal processing method is described.

Abstract: A method of determining filter coefficients of an equalizer circuit for equalizing a non-linear electronic system is described. The equalizer circuit includes a Volterra filter circuit. Further, an equalizer circuit for equalizing a non-linear electronic system and an electronic device are described.

Abstract: The present disclosure relates to a parallel filter structure for processing a signal. The parallel filter structure includes a signal input configured to receive a time and value discrete input signal. The parallel filter structure includes a feed forward equalizer circuit connected with the signal input for receiving the time and value discrete input signal. The parallel filter structure includes a decision feedback equalizer circuit connected with the signal input for receiving the time and value discrete input signal. The feed forward equalizer circuit and the decision feedback equalizer circuit together form a parallel circuit. Further, an oscilloscope and a method of processing a signal are provided.

Abstract: A bit error rate determination method for determining a bit error rate of an input signal is described, wherein the input signal is generated by a signal source, comprising: at least one of receiving and generating a first histogram of a time interval error associated with a first bounded jitter component of the input signal; at least one of receiving and generating random jitter data comprising information on a time interval error associated with a random jitter component of the input signal; and determining the bit error rate based on at least one of the first histogram and the random jitter data. Further, a measurement instrument is described.

Abstract: A method for recovering a clock signal from a data signal by using a clock recovery module is described. Edge timings of the data signal are accumulated. The edge timings accumulated are transformed into one reference bit period. A time offset for the reference bit period is determined. A reference clock signal is determined based on the time offset. The number of bits within a system clock of the clock recovery module is determined. The clock signal is recovered based on the reference clock signal and the number of bits. Further, a clock recovery module as well as a computer program are described.

Abstract: A jitter determination method for determining at least one jitter component of an input signal is described, wherein the input signal is generated by a signal source. The method comprises: receiving the input signal; determining a step response based on the decoded input signal, the step response being associated with at least the signal source; and determining a data dependent jitter signal based on the determined step response and based on the decoded input signal. Further, a measurement instrument is described.

Abstract: A jitter determination method for determining at least one jitter component of an input signal is described. The input signal is generated by a signal source, including: receiving the input signal; determining a step response based on the decoded input signal, the step response being associated with at least the signal source; and determining the at least one jitter component of the input signal based on at least one of the input signal and the determined step response. Further, a measurement instrument is described.

Abstract: A clock recovery method for recovering a clock signal from a data signal is described, wherein the data signal comprises a symbol sequence. The clock recovery method comprises the following steps: The data signal is received. At least two partial clock timings of a partial clock signal that is based on the data signal are determined. The number of symbols between the at least two partial clock timings is determined. Clock timings of the clock signal are determined based on the at least two partial clock timings and the number of symbols. Further, a clock recovery module is described.

Abstract: A jitter determination method for determining at least one jitter component of an input signal is described, wherein the input signal is generated by a signal source, comprising: receiving and/or generating probability data containing information on a collective probability density function of a random jitter component of the input signal and a other bounded uncorrelated jitter component of the input signal; determining a standard deviation of the random jitter component based on the probability data; determining a RJ probability density function associated with the random jitter component based on the standard deviation; and determining a OBUJ probability density function associated with the other bounded uncorrelated jitter component, wherein the OBUJ probability density function is determined based on the probability data and based on the probability density function that is associated with the random jitter component. Further, a measurement instrument is described.

Abstract: A clock timing recovery method for determining a clock timing of an input signal is described, wherein the input signal is generated by a signal source, comprising: receiving the input signal; determining signal edges of the input signal based on the received input signal; determining at least a first clock timing model parameter; determining at least one jitter component of the input signal; and determining a clock timing error associated with the at least one jitter component, wherein the clock timing error is determined based on the determined signal edges, the determined first clock timing model parameter and the determined jitter component. Moreover, a measurement instrument is described.

Abstract: A jitter determination method for determining at least one random jitter component of an input signal is described, wherein the input signal is generated by a signal source, comprising: receiving the input signal; determining a time interval error associated with the random jitter component; determining at least one statistical moment of the time interval error based on the determined time interval error, wherein the order of the statistical moment is two or larger; at least one of determining an impulse response based on the input signal and receiving the impulse response, the impulse response being associated with at least the signal source; and determining the standard deviation of the random jitter component based on at least one of the determined statistical moment and the determined impulse response. Moreover, a measurement instrument is described.

Abstract: A method for recovering a clock signal from a data signal by using a clock recovery module is described. At least one bit count of the data signal is received. At least one edge timing of the data signal is received. At least one cost function is formed that comprises the at least one bit count of the data signal and the at least one edge timing of the data signal. The at least one cost function is minimized with respect to at least one of a clock edge timing and a bit period. Further, a clock recovery module is described.

Abstract: A jitter decomposition method for decomposing several jitter and noise components contained in an input signal, wherein the input signal is generated by a signal source, is disclosed. The jitter decomposition method comprises: receiving the input signal; at least one of determining and receiving a reconstructed data dependent jitter signal; at least one of determining and receiving an impulse response, the impulse response being associated with at least the signal source; and determining at least a first statistical parameter being associated with a first jitter component or a first noise component in the input signal and a second statistical parameter being associated with a second jitter component or a second noise component in the input signal, the second jitter component or the second noise component being different from the first jitter component or the first noise component, respectively.

Abstract: A clock recovery method for recovering a clock signal from a data signal is described, wherein the data signal comprises a symbol sequence. The clock recovery method comprises the following steps: The data signal is received. At least two partial clock timings of a partial clock signal that is based on the data signal are determined. The number of symbols between the at least two partial clock timings is determined. Clock timings of the clock signal are determined based on the at least two partial clock timings and the number of symbols. Further, a clock recovery module is described.

Abstract: A clock timing recovery method for determining a clock timing of an input signal is described, wherein the input signal is generated by a signal source, comprising: receiving the input signal; determining signal edges of the input signal based on the received input signal; determining at least a first clock timing model parameter; determining at least one jitter component of the input signal; and determining a clock timing error associated with the at least one jitter component, wherein the clock timing error is determined based on the determined signal edges, the determined first clock timing model parameter and the determined jitter component. Moreover, a measurement instrument is described.