Abstract: A system and method is provided which predicts problematic areas for lithography in a circuit design, and more specifically, which uses modeling data from a modeling tool to accurately predict problematic lithographic areas. The method includes identifying surface heights of plurality of tiles of a modeled wafer, and mathematically mimicking a lithographic tool to determine best planes of focus for exposure for the plurality of tiles.

Abstract: A method and system to predict lithography focus error using chip topography data is disclosed. The chip topography data may be measured or simulated topography data. A plane is best fitted to the topography data, and residuals are computed. The residuals are then used to make a prediction regarding the focus error. The density ratio of metal to dielectric may also be used as a factor in determining the predicted focus error.

Abstract: A method and system to predict lithography focus error using chip topography data is disclosed. The chip topography data may be measured or simulated topography data. A plane is best fitted to the topography data, and residuals are computed. The residuals are then used to make a prediction regarding the focus error. The density ratio of metal to dielectric may also be used as a factor in determining the predicted focus error.

Abstract: A method and system to predict lithography focus error using chip topography data is disclosed. The chip topography data may be measured or simulated topography data. A plane is best fitted to the topography data, and residuals are computed. The residuals are then used to make a prediction regarding the focus error. The density ratio of metal to dielectric may also be used as a factor in determining the predicted focus error.

Abstract: A method and system to predict lithography focus error using chip topography data is disclosed. The chip topography data may be measured or simulated topography data. A plane is best fitted to the topography data, and residuals are computed. The residuals are then used to make a prediction regarding the focus error. The density ratio of metal to dielectric may also be used as a factor in determining the predicted focus error.

Abstract: A system and method is provided which predicts problematic areas for lithography in a circuit design, and more specifically, which uses modeling data from a modeling tool to accurately predict problematic lithographic areas. The method includes identifying surface heights of plurality of tiles of a modeled wafer, and mathematically mimicking a lithographic tool to determine best planes of focus for exposure for the plurality of tiles.

Abstract: A system and method is provided which predicts problematic areas for lithography in a circuit design, and more specifically, which uses modeling data from a modeling tool to accurately predict problematic lithographic areas. The method includes identifying surface heights of plurality of tiles of a modeled wafer, and mathematically mimicking a lithographic tool to determine best planes of focus for exposure for the plurality of tiles.

Abstract: A system and method is provided which predicts problematic areas for lithography in a circuit design, and more specifically, which uses modeling data from a modeling tool to accurately predict problematic lithographic areas. The method includes identifying surface heights of plurality of tiles of a modeled wafer, and mathematically mimicking a lithographic tool to determine best planes of focus for exposure for the plurality of tiles.

Abstract: A system and method is provided which predicts problematic areas for lithography in a circuit design, and more specifically, which uses modeling data from a modeling tool to accurately predict problematic lithographic areas. The method includes identifying surface heights of plurality of tiles of a modeled wafer, and mathematically mimicking a lithographic tool to determine best planes of focus for exposure for the plurality of tiles.

Abstract: A method and system to predict lithography focus error using chip topography data is disclosed. The chip topography data may be measured or simulated topography data. A plane is best fitted to the topography data, and residuals are computed. The residuals are then used to make a prediction regarding the focus error. The density ratio of metal to dielectric may also be used as a factor in determining the predicted focus error.

Abstract: An anti-reflective coating material, a microelectronic structure that includes an anti-reflective coating layer formed from the anti-reflective coating material and a related method for exposing a resist layer located over a substrate while using the anti-reflective coating layer provide for attenuation of secondary reflected vertical alignment beam radiation when aligning the substrate including the resist layer located thereover. Such enhanced vertical alignment provides for improved dimensional integrity of a patterned resist layer formed from the resist layer, as well as additional target layers that may be fabricated while using the resist layer as a mask.

Abstract: An anti-reflective coating material, a microelectronic structure that includes an anti-reflective coating layer formed from the anti-reflective coating material and a related method for exposing a resist layer located over a substrate while using the anti-reflective coating layer provide for attenuation of secondary reflected vertical alignment beam radiation when aligning the substrate including the resist layer located thereover. Such enhanced vertical alignment provides for improved dimensional integrity of a patterned resist layer formed from the resist layer, as well as additional target layers that may be fabricated while using the resist layer as a mask.

Abstract: A system and method is provided which predicts problematic areas for lithography in a circuit design, and more specifically, which uses modeling data from a modeling tool to accurately predict problematic lithographic areas. The method includes identifying surface heights of plurality of tiles of a modeled wafer, and mathematically mimicking a lithographic tool to determine best planes of focus for exposure for the plurality of tiles.

Abstract: A system and method is provided which predicts problematic areas for lithography in a circuit design, and more specifically, which uses modeling data from a modeling tool to accurately predict problematic lithographic areas. The method includes identifying surface heights of plurality of tiles of a modeled wafer, and mathematically mimicking a lithographic tool to determine best planes of focus for exposure for the plurality of tiles.

Abstract: An anti-reflective coating material, a microelectronic structure that includes an anti-reflective coating layer formed from the anti-reflective coating material and a related method for exposing a resist layer located over a substrate while using the anti-reflective coating layer provide for attenuation of secondary reflected vertical alignment beam radiation when aligning the substrate including the resist layer located thereover. Such enhanced vertical alignment provides for improved dimensional integrity of a patterned resist layer formed from the resist layer, as well as additional target layers that may be fabricated while using the resist layer as a mask.

Abstract: The invention relates to a method for determining processing image induced defects in the manufacture of semiconductor products such as wafers by analyzing the circuit design of the product mask and modifying a conventional test defect structure to mimic the product mask to incorporate one or more isolated or other features including product mask circuit features likely to cause processing image induced defects into the test defect structure.

Abstract: Methods of forming and using a mask having a mask substrate including a non-planar surface are disclosed. The non-planar surface includes at least one portion having a depth configured to compensate for topography on the surface of a semiconductor wafer.

Abstract: A method and apparatus are provided for improving the leveling and, consequently, the focusing of a substrate such as a wafer during the photolithography imaging procedure of a semiconductor manufacturing process. The invention performs a pre-scan of the wafer's topography and assigns importance values to different regions of the wafer surface. Exposure focus instructions are calculated based on the topography and importance values of the different regions and the wafer is then scanned and imaged based on the calculated exposure focus instructions.

Abstract: The invention relates to a method for determining processing image induced defects in the manufacture of semiconductor products such as wafers by analyzing the circuit design of the product mask and modifying a conventional test defect structure to mimic the product mask to incorporate one or more isolated or other features including product mask circuit features likely to cause processing image induced defects into the test defect structure.