Abstract: dsRNAi oligonucleotides can be used in methods for the treatment of NASH, preferably the advanced fibrotic and/or cirrhotic stages thereof, using dosage regimens comprising a loading phase followed by a maintenance phase.

Abstract: The present disclosure provides for a wrist arthroplasty system and method that enable an expedient surgical procedure, maintain wrist motion, and reduce the likelihood of implant loosening. The system includes a capitate implant, a radial implant, and a resection instrument. The capitate implant includes a convex head formed to interface with a concave socket of the radial implant. The capitate implant includes a single stem formed to be secured within a patient's capitate bone. The radial implant includes lips formed to increase wrist joint motion and to help prevent dislocation of the capitate implant from the radial implant. The resection instrument may be used in combination as a measurement tool for determining the proper implant size, a guide for properly positioning the implants, and a trial tool for testing trial implant components before securing the final radial and capitate implants.

Abstract: The present disclosure provides for a wrist arthroplasty system and method that enable an expedient surgical procedure, maintain wrist motion, and reduce the likelihood of implant loosening. The system includes a capitate implant, a radial implant, and a resection instrument. The capitate implant includes a convex head formed to interface with a concave socket of the radial implant. The capitate implant includes a single stem formed to be secured within a patient's capitate bone. The radial implant includes lips formed to increase wrist joint motion and to help prevent dislocation of the capitate implant from the radial implant. The resection instrument may be used in combination as a measurement tool for determining the proper implant size, a guide for properly positioning the implants, and a trial tool for testing trial implant components before securing the final radial and capitate implants.

Abstract: The present disclosure provides for a wrist arthroplasty system and method that enable an expedient surgical procedure, maintain wrist motion, and reduce the likelihood of implant loosening. The system includes a capitate implant, a radial implant, and a resection instrument. The capitate implant includes a convex head formed to interface with a concave socket of the radial implant. The capitate implant includes a single stem formed to be secured within a patient's capitate bone. The radial implant includes lips formed to increase wrist joint motion and to help prevent dislocation of the capitate implant from the radial implant. The resection instrument may be used in combination as a measurement tool for determining the proper implant size, a guide for properly positioning the implants, and a trial tool for testing trial implant components before securing the final radial and capitate implants.

Abstract: A method for determining an integrity of an execution of a code fragment is provided. The method includes identifying a reference signature for the code fragment within an abstracted representation of a program code comprising the code fragment. Further, the method includes executing the code fragment and determining a signature of the executed code fragment. The method includes comparing the signature with the reference signature.

Abstract: A method for determining an integrity of an execution of a code fragment is provided. The method includes identifying a reference signature for the code fragment within an abstracted representation of a program code comprising the code fragment. Further, the method includes executing the code fragment and determining a signature of the executed code fragment. The method includes comparing the signature with the reference signature.

Abstract: A semiconductor device is described. A channel area is arranged in a semiconductor substrate between a first contact area and a second contact area. A first programmable structure includes a first control structure. The first programmable structure is arranged such that a conductivity of a first section of the channel area depends on a voltage applicable to the first control structure of the first programmable structure and on an information value stored in the first programmable structure. A second programmable structure includes a second control structure. The second programmable structure is arranged such that a conductivity of a second section of the channel area depends on a voltage applicable to the second control structure of the second programmable structure and on an information value stored in the second programmable structure. The first section and the second section of the channel area are electrically connected in series between the first contact area and the second contact area.

Abstract: A semiconductor device is described. A channel area is arranged in a semiconductor substrate between a first contact area and a second contact area. A first programmable structure includes a first control structure. The first programmable structure is arranged such that a conductivity of a first section of the channel area depends on a voltage applicable to the first control structure of the first programmable structure and on an information value stored in the first programmable structure. A second programmable structure includes a second control structure. The second programmable structure is arranged such that a conductivity of a second section of the channel area depends on a voltage applicable to the second control structure of the second programmable structure and on an information value stored in the second programmable structure. The first section and the second section of the channel area are electrically connected in series between the first contact area and the second contact area.

Abstract: A semiconductor memory is disclosed having an electrically conductive region buried in a substrate, and having an array of first and second cells. The first cells are designed as memory cells each having a selection transistor and a storage capacitor and are connected to word lines and first bit lines. The second cells are designed as switchable contacts each having a selection transistor and a resistance element and are connected to a respective one of the word lines and to a second bit line. The resistance element includes a first electrode and a second electrode, which are conductively connected to one another. The second bit line makes it possible to apply a plate voltage to the buried conductive region in low-impedance fashion via the second cells.

Abstract: A device for reading out memory information storable in a memory has an integrator and a comparator. The memory provides, in a hold phase, a leakage current, and in a readout phase, a readout current. The readout current is dependent on the stored memory information. The integrator is adapted to integrate a quantity derived from the leakage current during the hold phase, and to provide a leakage voltage corresponding to an integrated leakage current. The integrator is further adapted to integrate a quantity derived from the readout current during the readout phase, and to provide a readout voltage corresponding to an integrated readout current. The comparator may compare the leakage voltage to the readout voltage and provide, in dependence on the comparison, a readout value corresponding to the memory information.

Abstract: A means of attachment for electrically contacting electronic components is disclosed. The means of attachment includes a carrier element and a number of elongated connecting elements. Each of the connecting elements is arranged on the carrier element and has an elongated body, which protrudes from the carrier element. Each of the connecting elements and the carrier element includes an electrically conductive surface.

Abstract: An overall plan for providing maintenance and technical services for businesses and plants, as broadly defined, includes generic procedures for the services written as a manual of standard practices. A knowledge base or experience database of data and people is utilized, and both hardware and software tools are selected and used in providing the services.

Abstract: A metallization surface (5), which acts as an etching stop layer during the production of openings (4) in a passivation layer (3) applied to its upper face and protects an interconnect structure (6) arranged underneath it, is arranged in an uppermost metallization level (1). A further opening is produced in the metal surface (5), through which a focused ion beam is aimed at the interconnect structure (6) in order to connect interconnects to one another and/or to interrupt at least one interconnect. The wiring of the integrated circuit can thus be varied individually, starting from identically produced semiconductor chips.

Abstract: The source area (3) is highly doped, like the channel area, for the same conductance type. The drain area (4) is doped for the opposite conductance type. This results in a saving of area since the source connection (S) can at the same time be used as the well connection or substrate connection.

Abstract: A receiver circuit arrangement includes a receiver circuit an input for receiving an input signal an output for outputting an output signal and an inverter circuit with switching transistors. The input signal is fed to the receiver circuit. At least one control transistor is connected in series with the switching transistors. A control circuit is connected on the input side to a terminal for a reference voltage and on the output side to the control terminal of the control transistor of the inverter circuit. The control circuit is designed such that the control transistor is driven by the regulating switching circuit in the event of deviations of the reference voltage from a voltage value in a reference operating state with a control voltage that deviates with respect to the reference operating state.

Abstract: An integrated circuit with electrostatic discharge protection includes a first transistor with a source terminal, a drain terminal and a gate terminal, and a second transistor with a source terminal, a drain terminal and a gate terminal. The gate terminal for each of the first and second transistors is connected to the drain terminal. The first transistor is connected in series with the second transistor by one of the drain and source terminals of the first transistor being connected to one of the drain and source terminals of the second transistor. The series circuit formed by the transistors is connected to an input terminal of the integrated circuit or to a supply terminal and a terminal that applies the reference potential of the integrated circuit. The series circuit of the transistors is dimensioned by the number of transistors and the setting of the channel length and channel width ratios of the transistors.

Abstract: An integrated semiconductor memory includes programmable elements, which are arranged in a continuous region on a chip area of the integrated semiconductor memory. Operating parameters, for example, word line addresses of defective word lines are stored in the programmable elements in a compressed data format during the fabrication process of the integrated semiconductor memory. Upon activation of the integrated semiconductor memory, the compressed data are read out by a read-out circuit and fed to a decompression circuit. The decompression circuit generates, from a bit sequence of the compressed data with the aid of a decompression algorithm, a bit sequence of decompressed data which are evaluated by a control circuit. The storage of the operating parameters in the compressed data format and the arrangement of the programmable elements in a compact region significantly reduce the space requirement on the semiconductor chip.

Abstract: An integrated semiconductor memory device includes a first memory zone, a second memory zone, first address connections and a second address connection. A second address signal present at the second address connection specifies the access to the first or second memory zone, whereas it is specified via first address signals at the first address connections which memory cell is accessed within the first or second memory zone. In a first memory configuration, all address connections are driven externally with address signals and the access to a memory cell in the first or second memory zone is controlled. In a second memory configuration, only the first address connections are driven externally whereas a signaling bit in a mode register regulates the access to the first or second memory zone. This provides for access to the second memory zone even if there is no possibility of externally driving the second address connection.

Abstract: An integrated circuit includes a voltage generator with a first controllable resistor and a second controllable resistor, through which a first input terminal that applies a first voltage potential and a second input terminal that applies a second voltage potential can be connected to an output terminal that generates an output voltage. In a manner dependent on the output voltage, a first comparator circuit generates a first control signal to control the first controllable resistor, and a second comparator circuit generates a second control signal to control the second controllable resistor. A control unit evaluates the control signals generated by the comparator circuits and drives the first and second controllable resistors of the voltage generator in such a way that in each case only one of the two controllable resistors has a low-resistance state.

Abstract: An integrated circuit includes a first and a second amplifier circuit (10, 20), which are in each case driven by an input signal (Vin) having a high and a low signal level and a reference signal (Vref) having a constant signal level and, on the output side (D11, D21) generate a first control signal (S1) and a second control signal (S2). The control signals (S1, S2) are generated independently of one another and are used to regulate a first controllable resistor (31) and a second controllable resistor (32) of a third amplifier circuit (30). Depending on the resistance value of the first and second controllable resistors (31, 32) of the third amplifier circuit, an output signal (Vout) that is amplified in comparison with the input signal (Vin) can be generated at an output terminal (A). The integrated circuit can be used as an input amplifier of an integrated semiconductor memory and permits an adaptive behavior of the input amplifier with regard to fluctuations of the average absolute input signal level.