Abstract: An ESD protection circuit includes a silicon controlled rectifier (SCR) including a first conduction path between a first node and a second node and a clamp circuit coupled to a control terminal of the SCR. The clamp circuit is part of a second conduction path between the first node and the second node. During an ESD event, the clamp circuit conduct an ESD current until a threshold IV point is reached. The clamp circuit triggers the SCR, which then acts as a snapback device to conduct the ESD current at a lower voltage.

Abstract: An ESD protection circuit includes a silicon controlled rectifier (SCR) including a first conduction path between a first node and a second node and a clamp circuit coupled to a control terminal of the SCR. The clamp circuit is part of a second conduction path between the first node and the second node. During an ESD event, the clamp circuit conduct an ESD current until a threshold IV point is reached. The clamp circuit triggers the SCR, which then acts as a snapback device to conduct the ESD current at a lower voltage.

Abstract: An interface device for a purging unit for purging a wafer container with a purging gas, which comprises a contact piece for contacting a purging interface of a wafer container, wherein the contact piece is movably arranged in the purging unit and has a gas passage in its interior. A corresponding interface device is provided. The object is to specify an interface device which, when the wafer container is coupled to the purging unit, makes it possible to seal a gas inlet or a gas outlet, to introduce or to discharge a purging gas into the wafer container, thereby compensating for and adapting to vertical and horizontal movements, preventing wear, and fulfilling a passive coupling and sealing function as well as offering maximum durability and reliability. This is achieved by a contact piece which is suspended directly or indirectly in the purging unit by means of a spring device.

Abstract: An interface device for a purging unit for purging a wafer container with a purging gas, which comprises a contact piece for contacting a purging interface of a wafer container, wherein the contact piece is movably arranged in the purging unit and has a gas passage in its interior. A corresponding interface device is provided. The object is to specify an interface device which, when the wafer container is coupled to the purging unit, makes it possible to seal a gas inlet or a gas outlet, to introduce or to discharge a purging gas into the wafer container, thereby compensating for and adapting to vertical and horizontal movements, preventing wear, and fulfilling a passive coupling and sealing function as well as offering maximum durability and reliability. This is achieved by a contact piece which is suspended directly or indirectly in the purging unit by means of a spring device.

Abstract: Described is an apparatus which comprises: a pad; a first transistor coupled in series with a second transistor and coupled to the pad; and a self-biasing circuit to bias the first transistor such that the first transistor is to be weakly biased during an electrostatic discharge (ESD) event. Described is also an apparatus which comprises: a first transistor; and a first local ballast resistor formed of a trench contact (TCN) layer, the first local ballast resistor having a first terminal coupled to either the drain or source terminal of the first transistor.

Abstract: Described is an apparatus which comprises: a pad; a first transistor coupled in series with a second transistor and coupled to the pad; and a self-biasing circuit to bias the first transistor such that the first transistor is to be weakly biased during an electrostatic discharge (ESD) event. Described is also an apparatus which comprises: a first transistor; and a first local ballast resistor formed of a trench contact (TCN) layer, the first local ballast resistor having a first terminal coupled to either the drain or source terminal of the first transistor.

Abstract: Various embodiments described below relate to an ESD protection device that includes a voltage controlled shunt (e.g., a transistor) to selectively shunt energy of an incoming ESD pulse away from a circuit that includes a semiconductor device to be protected. In some embodiments, the ESD protection device includes a power up detection element to determine whether the circuit has powered up. If the circuit is powered up, the power up detection element prevents inadvertent triggering of the ESD protection device.

Abstract: Various embodiments described below relate to an ESD protection device that includes a voltage controlled shunt (e.g., a transistor) to selectively shunt energy of an incoming ESD pulse away from a circuit that includes a semiconductor device to be protected. In some embodiments, the ESD protection device includes a power up detection element to determine whether the circuit has powered up. If the circuit is powered up, the power up detection element prevents inadvertent triggering of the ESD protection device.

Abstract: Various embodiments described below relate to an ESD protection device that includes a voltage controlled shunt (e.g., a transistor) to selectively shunt energy of an incoming ESD pulse away from a circuit that includes a semiconductor device to be protected. In some embodiments, the ESD protection device includes a power up detection element to determine whether the circuit has powered up. If the circuit is powered up, the power up detection element prevents inadvertent triggering of the ESD protection device.