Abstract: A circuit for reducing the latch-up sensitivity in complementary MOS technology includes a semiconductor substrate of a second conduction type. A first MOS transistor of a first complementary conduction type is disposed in the semiconductor substrate and has a source structure. A well of the first conduction type is disposed in the semiconductor substrate. A second MOS transistor of the second conduction type is disposed in the well and has a source structure. The semiconductor substrate and the source structure of the first transistor are connected to a first supply potential. The well and the source structure of the second transistor are connected to a second supply potential. A third transistor of the first conduction type is disposed in the semiconductor substrate between the first and second transistors. The third transistor has a gate connected to the first supply potential, a drain structure connected to the second supply potential, and a source structure connected to an output.