Patents by Inventor Bernhard Wolfgang Ruck
Bernhard Wolfgang Ruck has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20240128851Abstract: A driver includes a low-resistance charging path between a supply voltage rail and a first output node, a high-resistance charging path between the supply voltage rail and the first output node, an inverter coupled to the first output node and configured to enable and disable the low-resistance charging path, and a high-resistance discharging path between the first output node and a second output node. The first output node is coupled to a control terminal of a pass gate transistor in some implementations. The low-resistance charging path charges a voltage on the first output node to a threshold voltage of the pass gate transistor, and the high-resistance charging path charges the voltage on the first output node greater than the threshold voltage of the pass gate transistor. The high-resistance discharging path discharges the voltage on the first output node.Type: ApplicationFiled: December 21, 2023Publication date: April 18, 2024Inventors: Bernhard Wolfgang RUCK, Ruediger KUHN, Oliver NEHRIG
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Patent number: 11901803Abstract: A driver includes a low-resistance charging path between a supply voltage rail and a first output node, a high-resistance charging path between the supply voltage rail and the first output node, an inverter coupled to the first output node and configured to enable and disable the low-resistance charging path, and a high-resistance discharging path between the first output node and a second output node. The first output node is coupled to a control terminal of a pass gate transistor in some implementations. The low-resistance charging path charges a voltage on the first output node to a threshold voltage of the pass gate transistor, and the high-resistance charging path charges the voltage on the first output node greater than the threshold voltage of the pass gate transistor. The high-resistance discharging path discharges the voltage on the first output node.Type: GrantFiled: December 23, 2021Date of Patent: February 13, 2024Assignee: Texas Instruments IncorporatedInventors: Bernhard Wolfgang Ruck, Ruediger Kuhn, Oliver Nehrig
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Publication number: 20230208291Abstract: A driver includes a low-resistance charging path between a supply voltage rail and a first output node, a high-resistance charging path between the supply voltage rail and the first output node, an inverter coupled to the first output node and configured to enable and disable the low-resistance charging path, and a high-resistance discharging path between the first output node and a second output node. The first output node is coupled to a control terminal of a pass gate transistor in some implementations. The low-resistance charging path charges a voltage on the first output node to a threshold voltage of the pass gate transistor, and the high-resistance charging path charges the voltage on the first output node greater than the threshold voltage of the pass gate transistor. The high-resistance discharging path discharges the voltage on the first output node.Type: ApplicationFiled: December 23, 2021Publication date: June 29, 2023Inventors: Bernhard Wolfgang RUCK, Ruediger KUHN, Oliver NEHRIG
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Publication number: 20220374035Abstract: A system includes a digital controller in a voltage regulator. The system also includes a passgate array including two or more passgate transistors, where the passgate array is configured to provide a load current to a load, and where the digital controller is configured to activate and deactivate each passgate transistor in the passgate array. The system also includes a feedback loop configured to provide an error signal to the digital controller, the error signal based on a difference between an output voltage of the voltage regulator and a programmed voltage for the voltage regulator. The digital controller is configured to activate or deactivate a passgate transistor based at least in part on the error signal. The digital controller is also configured to activate at least one passgate transistor and deactivate at least one passgate transistor responsive to a clock cycle.Type: ApplicationFiled: May 18, 2021Publication date: November 24, 2022Inventors: Johannes GERBER, Asif QAIYUM, Fraj GHARIB, Christian Josef SICHERT, Ruediger KUHN, Frank DORNSEIFER, Bernhard Wolfgang RUCK
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Patent number: 10560112Abstract: An analog-to-digital converter (ADC) includes a digital-to-analog converter (DAC) that has a configurable capacitor array. Based on measurements of differential nonlinearity (DNL) and/or integral nonlinearity (INL) error by an external test computer system, an order for use of the DAC's capacitors can be determined so as to reduce DNL error aggregation, also called INL. The DAC includes a switch matrix that can be programmed by programming data supplied by the test computer system.Type: GrantFiled: April 3, 2019Date of Patent: February 11, 2020Assignee: TEXAS INSTRUMENTS INCORPORATEDInventors: Thomas Fuchs, Rudiger Kuhn, Bernhard Wolfgang Ruck
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Publication number: 20190229743Abstract: An analog-to-digital converter (ADC) includes a digital-to-analog converter (DAC) that has a configurable capacitor array. Based on measurements of differential nonlinearity (DNL) and/or integral nonlinearity (INL) error by an external test computer system, an order for use of the DAC's capacitors can be determined so as to reduce DNL error aggregation, also called INL. The DAC includes a switch matrix that can be programmed by programming data supplied by the test computer system.Type: ApplicationFiled: April 3, 2019Publication date: July 25, 2019Inventors: Thomas Fuchs, Rudiger Kuhn, Bernhard Wolfgang Ruck
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Patent number: 10298250Abstract: An analog-to-digital converter (ADC) includes a digital-to-analog converter (DAC) that has a configurable capacitor array. Based on measurements of differential nonlinearity (DNL) and/or integral nonlinearity (INL) error by an external test computer system, an order for use of the DAC's capacitors can be determined so as to reduce DNL error aggregation, also called INL. The DAC includes a switch matrix that can be programmed by programming data supplied by the test computer system.Type: GrantFiled: April 10, 2017Date of Patent: May 21, 2019Assignee: TEXAS INSTRUMENTS INCORPORATEDInventors: Thomas Fuchs, Rudiger Kuhn, Bernhard Wolfgang Ruck
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Publication number: 20170250699Abstract: An analog-to-digital converter (ADC) includes a digital-to-analog converter (DAC) that has a configurable capacitor array. Based on measurements of differential nonlinearity (DNL) and/or integral nonlinearity (INL) error by an external test computer system, an order for use of the DAC's capacitors can be determined so as to reduce DNL error aggregation, also called INL. The DAC includes a switch matrix that can be programmed by programming data supplied by the test computer system.Type: ApplicationFiled: April 10, 2017Publication date: August 31, 2017Inventors: Thomas Fuchs, Rudiger Kuhn, Bernhard Wolfgang Ruck
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Patent number: 9654131Abstract: An analog-to-digital converter (ADC) includes a digital-to-analog converter (DAC) that has a configurable capacitor array. Based on measurements of differential nonlinearity (DNL) and/or integral nonlinearity (INL) error by an external test computer system, an order for use of the DAC's capacitors can be determined so as to reduce DNL error aggregation, also called INL. The DAC includes a switch matrix that can be programmed by programming data supplied by the test computer system.Type: GrantFiled: February 26, 2016Date of Patent: May 16, 2017Assignee: TEXAS INSTRUMENTS DEUTSCHLAND GMBHInventors: Thomas Fuchs, RĂ¼diger Kuhn, Bernhard Wolfgang Ruck
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Patent number: 8373459Abstract: An integrated circuit provides a power on reset signal with respect to a supply voltage level supplying the electronic device. The integrated circuit comprises a bias current generating stage having a first current mirror and an output stage having first, second and third series connected MOS transistors. A connection between the second MOS transistor and the third MOS transistor forms a POR output node. A gate of the second MOS transistor and a gate of the third MOS transistor are coupled to each other and to the first current mirror. This allows a current through the third MOS transistor when the supply voltage is higher than a first MOS transistor threshold and a current through the second MOS transistor only when the supply voltage is greater than or equal to the sum of the first MOS transistor threshold and a second MOS transistor threshold voltage.Type: GrantFiled: January 12, 2011Date of Patent: February 12, 2013Assignee: Texas Instruments IncorporatedInventors: Santiago Iriarte Garcia, Johannes Gerber, Bernhard Wolfgang Ruck
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Publication number: 20120286833Abstract: An integrated circuit provides a power on reset signal with respect to a supply voltage level supplying the electronic device. The integrated circuit comprises a bias current generating stage having a first current mirror and an output stage having first, second and third series connected MOS transistors. A connection between the second MOS transistor and the third MOS transistor forms a POR output node. A gate of the second MOS transistor and a gate of the third MOS transistor are coupled to each other and to the first current mirror. This allows a current through the third MOS transistor when the supply voltage is higher than a first MOS transistor threshold and a current through the second MOS transistor only when the supply voltage is greater than or equal to the sum of the first MOS transistor threshold and a second MOS transistor threshold voltage.Type: ApplicationFiled: January 12, 2011Publication date: November 15, 2012Applicant: TEXAS INSTRUMENTS INCORPORATEDInventors: Santiago Iriarte Garcia, Johannes Gerber, Bernhard Wolfgang Ruck
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Patent number: 7893734Abstract: An integrated circuit provides a power on reset signal with respect to a supply voltage level supplying the electronic device. The integrated circuit comprises a bias current generating stage having a first current mirror and an output stage having first, second and third series connected MOS transistors. A connection between the second MOS transistor and the third MOS transistor forms a POR output node. A gate of the second MOS transistor and a gate of the third MOS transistor are coupled to each other and to the first current mirror. This allows a current through the third MOS transistor when the supply voltage is higher than a first MOS transistor threshold and a current through the second MOS transistor only when the supply voltage is greater than or equal to the sum of the first MOS transistor threshold and a second MOS transistor threshold voltage.Type: GrantFiled: October 8, 2008Date of Patent: February 22, 2011Assignee: Texas Instruments IncorporatedInventors: Santiago Iriarte Garcia, Johannes Gerber, Bernhard Wolfgang Ruck
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Patent number: 7786920Abstract: A method for controlling a successive approximation register analog to digital converter comprising connecting a first side of a capacitor to a first comparator input, during a sampling phase connecting the first side of a capacitor to an input and connecting a second side of the capacitor to a mid-voltage, following the sampling phase disconnecting the first side of the capacitor from the input and disconnecting the second side of the capacitor from the mid-voltage and autozeroing the comparator.Type: GrantFiled: September 4, 2008Date of Patent: August 31, 2010Assignee: Texas Instruments IncorporatedInventors: Johannes Gerber, Bernhard Wolfgang Ruck
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Publication number: 20090121754Abstract: An integrated circuit provides a power on reset signal with respect to a supply voltage level supplying the electronic device. The integrated circuit comprises a bias current generating stage having a first current mirror and an output stage having first, second and third series connected MOS transistors. A connection between the second MOS transistor and the third MOS transistor forms a POR output node. A gate of the second MOS transistor and a gate of the third MOS transistor are coupled to each other and to the first current mirror. This allows a current through the third MOS transistor when the supply voltage is higher than a first MOS transistor threshold and a current through the second MOS transistor only when the supply voltage is greater than or equal to the sum of the first MOS transistor threshold and a second MOS transistor threshold voltage.Type: ApplicationFiled: October 8, 2008Publication date: May 14, 2009Inventors: Santiago Iriarte Garcia, Johannes Gerber, Bernhard Wolfgang Ruck
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Publication number: 20090066556Abstract: A method for controlling a successive approximation register analog to digital converter comprising connecting a first side of a capacitor to a first comparator input, during a sampling phase connecting the first side of a capacitor to an input and connecting a second side of the capacitor to a mid-voltage, following the sampling phase disconnecting the first side of the capacitor from the input and disconnecting the second side of the capacitor from the mid-voltage and autozeroing the comparator.Type: ApplicationFiled: September 4, 2008Publication date: March 12, 2009Inventors: Johannes Gerber, Bernhard Wolfgang Ruck
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Publication number: 20090058493Abstract: An electronic device with a supply voltage level converter converts a signal from a first low supply voltage level to a second high supply voltage level includes; a first pair of cross coupled MOS transistors compliant with the second supply voltage level, each having a source coupled to the second supply voltage level and providing complementary output signals at respective drains; driven by a second pair of common gate MOS transistors compliant with the second supply voltage; driven by a third pair of common gate MOS transistors compliant with the first voltage level; and driven by first and second inverters coupled in a chain and supplied by the first supply voltage level, each having an output connected to the source of a transistor in a third pair.Type: ApplicationFiled: August 25, 2008Publication date: March 5, 2009Inventors: Matthias Arnold, Johannes Gerber, Bernhard Wolfgang Ruck
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Publication number: 20080272831Abstract: A charge pump CMOS circuit comprises a differential input stage with two parallel circuit branches. Each of the parallel circuit branches has a diode-connected MOS transistor connected in series with a complementary input MOS transistor. There is a common tail current source for both circuit branches. The diode-connected MOS transistors each have their gate/drain node connected to corresponding current sources. The charge pump CMOS circuit is suitable for use in an oscillator.Type: ApplicationFiled: April 2, 2008Publication date: November 6, 2008Inventors: Bernhard Wolfgang Ruck, Johannes Gerber