Patents by Inventor Bernhard Wotruba
Bernhard Wotruba has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 11750960Abstract: A microphone includes an amplifier coupled to an input node of the microphone; a shock detector coupled to the input node of the microphone; and a recovery circuit having an input coupled to an output of the shock detector, and an output coupled to the input of the microphone.Type: GrantFiled: October 20, 2021Date of Patent: September 5, 2023Assignee: Infineon Technologies AGInventors: Jose Luis Ceballos, Hong Chen, Fulvio Ciciotti, Andreas Wiesbauer, Bernhard Wotruba
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Publication number: 20230121912Abstract: A microphone includes an amplifier coupled to an input node of the microphone; a shock detector coupled to the input node of the microphone; and a recovery circuit having an input coupled to an output of the shock detector, and an output coupled to the input of the microphone.Type: ApplicationFiled: October 20, 2021Publication date: April 20, 2023Inventors: Jose Luis Ceballos, Hong Chen, Fulvio Ciciotti, Andreas Wiesbauer, Bernhard Wotruba
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Patent number: 10734798Abstract: A circuit includes a first regulation module, second regulation module, first monitoring module, and second monitoring module. The first regulation module is configured to generate, from a supply voltage, a first voltage. The second regulation module is configured to generate, from a first voltage, a second voltage that is less than the first voltage. The first monitoring module is configured to generate a first warning signal when the first voltage exceeds a first threshold and to generate the first warning signal when a first testing voltage exceeds the first threshold. The second monitoring module is configured to generate a second warning signal when the second voltage exceeds a second threshold and to generate the second warning signal when a second testing voltage exceeds the second threshold.Type: GrantFiled: May 18, 2018Date of Patent: August 4, 2020Assignee: Infineon Technologies AGInventors: Cristian Garbossa, Bernhard Wotruba
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Publication number: 20190356126Abstract: A circuit includes a first regulation module, second regulation module, first monitoring module, and second monitoring module. The first regulation module is configured to generate, from a supply voltage, a first voltage. The second regulation module is configured to generate, from a first voltage, a second voltage that is less than the first voltage. The first monitoring module is configured to generate a first warning signal when the first voltage exceeds a first threshold and to generate the first warning signal when a first testing voltage exceeds the first threshold. The second monitoring module is configured to generate a second warning signal when the second voltage exceeds a second threshold and to generate the second warning signal when a second testing voltage exceeds the second threshold.Type: ApplicationFiled: May 18, 2018Publication date: November 21, 2019Inventors: Cristian Garbossa, Bernhard Wotruba
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Patent number: 10411883Abstract: Devices for sampling a plurality of input signals are provided, wherein a sampling device is controlled to sample the input signals in a random order with additional delays. Other embodiments relate to voltage monitoring systems and corresponding methods.Type: GrantFiled: October 18, 2016Date of Patent: September 10, 2019Assignee: Infineon Technologies AGInventors: Martin Pernull, Andreas Kalt, Gerhard Pichler, Franz Wachter, Bernhard Wotruba
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Publication number: 20170118012Abstract: Devices for sampling a plurality of input signals are provided, wherein a sampling device is controlled to sample the input signals in a random order with additional delays. Other embodiments relate to voltage monitoring systems and corresponding methods.Type: ApplicationFiled: October 18, 2016Publication date: April 27, 2017Inventors: Martin Pernull, Andreas Kalt, Gerhard Pichler, Franz Wachter, Bernhard Wotruba
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Patent number: 8013475Abstract: An integrated circuit arrangement includes a semiconductor body having a substrate and at least one substrate terminal. At least one semiconductor component is integrated in the semiconductor body and is connected between a first supply terminal and a second supply terminal. The first supply potential is higher than the second supply potential during normal operation of the semiconductor component and the first supply potential is lower than the second supply potential during reverse voltage operation of the semiconductor component. A switch is adapted to couple at least one of the substrate terminals to the first supply terminal during reverse voltage operation and to the second supply terminal during normal operation.Type: GrantFiled: December 27, 2007Date of Patent: September 6, 2011Assignee: Infineon Technologies AGInventors: Bernhard Wotruba, Andrea Logiudice, Andrea Scenini, Salvatore Pastorina
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Publication number: 20080225454Abstract: An integrated circuit arrangement includes a semiconductor body having a substrate and at least one substrate terminal. At least one semiconductor component is integrated in the semiconductor body and is connected between a first supply terminal and a second supply terminal. The first supply potential is higher than the second supply potential during normal operation of the semiconductor component and the first supply potential is lower than the second supply potential during reverse voltage operation of the semiconductor component. A switch is adapted to couple at least one of the substrate terminals to the first supply terminal during reverse voltage operation and to the second supply terminal during normal operation.Type: ApplicationFiled: December 27, 2007Publication date: September 18, 2008Inventors: Bernhard Wotruba, Andrea Logiudice
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Patent number: 7411770Abstract: A circuit arrangement includes a first semiconductor switch and at least one second semiconductor switch, each of them having a control terminal and a first and second load terminal, and with an overvoltage protection arrangement for the at least two semiconductor switches. The overvoltage protection arrangement comprises a voltage limiting unit with a first and a second terminal, whose first terminal is connected to a central circuit node, whose second terminal is connected to a terminal for a reference potential, and which is configured so that it conducts current when a threshold voltage is applied between the first and second load terminals. The central circuit node is coupled to the first load terminals of the semiconductor switches. The overvoltage protection arrangement further comprises a first actuating circuit for the first semiconductor switch and a second actuating circuit for the at least one second semiconductor switch.Type: GrantFiled: February 28, 2006Date of Patent: August 12, 2008Assignee: Infineon Technologies AGInventors: Andrea Logiudice, Salvatore Giovanni Pastorina, Andrea Scenini, Bernhard Wotruba
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Publication number: 20080002324Abstract: A circuit arrangement includes plural semiconductor switches, at least one overvoltage protection arrangement and a coupling circuit. Each of a first semiconductor switch and a second semiconductor switch has a control terminal and first and second load terminals. The at least one overvoltage protection arrangement provides overvoltage protection to the semiconductor switches. The coupling circuit is operable to selectively couple the control terminals of at least two of the at least two semiconductor switches.Type: ApplicationFiled: April 2, 2007Publication date: January 3, 2008Applicant: Infineon Technologies Austria AGInventors: Andrea Logiudice, Salvatore Pastorina, Andrea Scenini, Bernhard Wotruba
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Publication number: 20070200546Abstract: The invention relates to a reference voltage generating circuit comprising: a voltage source circuit (10) which is constructed for providing at an output (15) a first reference voltage (Vbe/a) which is proportional to the voltage (Vbe) across a pn junction, polarized in the forward direction, of a bipolar component (11) and which is lower than this voltage, an amplifier arrangement (2) having a first and second input (25, 26), an output (27) at which an output voltage (Vout) is available, a differential amplifier stage (20) which has at least two semiconductor components (21, 22; 121, 122), and an output stage (30), the first reference voltage (Vbe/a) being supplied to the first input (25), the output (27) being fed back to the second input (26) and the amplifier arrangement having an offset which is proportional to the thermal voltage of a semiconductor material of the at least two semiconductor components (21, 22; 121, 122) of the differential amplifier stage (20) and wherein a second reference voltageType: ApplicationFiled: July 18, 2006Publication date: August 30, 2007Applicant: Infineon Technologies AGInventors: Andrea Logiudice, Bernhard Wotruba
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Publication number: 20070103830Abstract: A circuit arrangement includes a first semiconductor switch and at least one second semiconductor switch, each of them having a control terminal and a first and second load terminal, and with an overvoltage protection arrangement for the at least two semiconductor switches. The overvoltage protection arrangement comprises a voltage limiting unit with a first and a second terminal, whose first terminal is connected to a central circuit node, whose second terminal is connected to a terminal for a reference potential, and which is configured so that it conducts current when a threshold voltage is applied between the first and second load terminals. The central circuit node is coupled to the first load terminals of the semiconductor switches. The overvoltage protection arrangement further comprises a first actuating circuit for the first semiconductor switch and a second actuating circuit for the at least one second semiconductor switch.Type: ApplicationFiled: February 28, 2006Publication date: May 10, 2007Applicant: Infineon Technologies AGInventors: Andrea Logiudice, Salvatore Pastorina, Andrea Scenini, Bernhard Wotruba