Abstract: Disclosed is a method for driving a transistor device and an electronic circuit that includes a transistor device. The method includes driving the transistor device based on a drive signal such that the transistor device is driven in an on-state when the drive signal has an on-level and an off-state when the drive signal has an off-level. Driving the transistor device in the off-state includes: operating the transistor device in a first off-state after the drive signal changes from the on-level to the off-level; after the first off-state, operating the transistor device in a second off-state different from the first off-state; and after the second off-state, operating the transistor device in a third off-state different from the second off-state if the off-level of the drive signal prevails longer than a predefined maximum time period.

Abstract: Circuits and devices for bidirectional normally-off switches are described. A circuit for a bidirectional normally-off switch includes a depletion mode transistor and an enhancement mode transistor. The depletion mode transistor includes a first source/drain node, a second source/drain node, a first gate, and a second gate. The enhancement mode transistor includes a third source/drain node and a fourth source/drain node, and a third gate. The third source/drain node is coupled to the first source/drain node.

Abstract: Disclosed is a method for driving a transistor device and an electronic circuit that includes a transistor device. The method includes driving the transistor device based on a drive signal such that the transistor device is driven in an on-state when the drive signal has an on-level and an off-state when the drive signal has an off-level. Driving the transistor device in the off-state includes: operating the transistor device in a first off-state after the drive signal changes from the on-level to the off-level; after the first off-state, operating the transistor device in a second off-state different from the first off-state; and after the second off-state, operating the transistor device in a third off-state different from the second off-state if the off-level of the drive signal prevails longer than a predefined maximum time period.

Abstract: Circuits and devices for bidirectional normally-off switches are described. A circuit for a bidirectional normally-off switch includes a depletion mode transistor and an enhancement mode transistor. The depletion mode transistor includes a first source/drain node, a second source/drain node, a first gate, and a second gate. The enhancement mode transistor includes a third source/drain node and a fourth source/drain node, and a third gate. The third source/drain node is coupled to the first source/drain node.

Abstract: In accordance with an embodiment, a circuit including: a gate driver coupled to a first supply terminal and to an output terminal, the output terminal configured to be coupled to a gate of a switching transistor via an inductive element, the gate driver configured to receive a switching signal; provide a first gate activation voltage at the output terminal with a first output resistance when the switching signal transitions from a first state to a second state; provide the first gate activation voltage at the output terminal with a second output resistance after a first time of providing the first gate activation voltage at the output terminal with the first output resistance, the second output resistance being larger than the first output resistance; and provide a first gate deactivation voltage at the output terminal when the switching signal transitions from the second state to the first state.

Abstract: In accordance with an embodiment, a circuit including: a gate driver coupled to a first supply terminal and to an output terminal, the output terminal configured to be coupled to a gate of a switching transistor via an inductive element, the gate driver configured to receive a switching signal; provide a first gate activation voltage at the output terminal with a first output resistance when the switching signal transitions from a first state to a second state; provide the first gate activation voltage at the output terminal with a second output resistance after a first time of providing the first gate activation voltage at the output terminal with the first output resistance, the second output resistance being larger than the first output resistance; and provide a first gate deactivation voltage at the output terminal when the switching signal transitions from the second state to the first state.

Abstract: Circuits and devices for bidirectional normally-off switches are described. A circuit for a bidirectional normally-off switch includes a depletion mode transistor and an enhancement mode transistor. The depletion mode transistor includes a first source/drain node, a second source/drain node, a first gate, and a second gate. The enhancement mode transistor includes a third source/drain node and a fourth source/drain node, and a third gate. The third source/drain node is coupled to the first source/drain node.

Abstract: In accordance with an embodiment, a method includes conducting a reverse current through a first switch that includes a normally-on transistor coupled in series with a normally-off transistor between a first switch node and a second switch node. While conducting the reverse current, the first switch is turned-off by turning-off the normally-off transistor via a control node of the normally-off transistor and reducing a drive voltage of the normally-on transistor by decreasing a voltage between the control node of the normally-on transistor and a reference node of the normally-on transistor. After turning-off the first switch, a second switch coupled to the first switch is turned on.

Abstract: Circuits and devices for bidirectional normally-off switches are described. A circuit for a bidirectional normally-off switch includes a depletion mode transistor and an enhancement mode transistor. The depletion mode transistor includes a first source/drain node, a second source/drain node, a first gate, and a second gate. The enhancement mode transistor includes a third source/drain node and a fourth source/drain node, and a third gate. The third source/drain node is coupled to the first source/drain node.

Abstract: In accordance with an embodiment, a method includes conducting a reverse current through a first switch that includes a normally-on transistor coupled in series with a normally-off transistor between a first switch node and a second switch node. While conducting the reverse current, the first switch is turned-off by turning-off the normally-off transistor via a control node of the normally-off transistor and reducing a drive voltage of the normally-on transistor by decreasing a voltage between the control node of the normally-on transistor and a reference node of the normally-on transistor. After turning-off the first switch, a second switch coupled to the first switch is turned on.

Abstract: In accordance with an embodiment, a circuit includes a first driver having a first output configured to be coupled to a control node of a normally-off transistor. The first driver is configured to drive a first switching signal at the first output in a cascode mode and configured to drive a first constant voltage at the first output in a direct drive mode. The circuit further includes a second driver having a second output configured to be coupled to a control node of a normally-on transistor that has a second load path terminal coupled to a first load path terminal of the normally-off transistor. The second driver is configured to drive a second switching signal at the second output in the direct drive mode.

Abstract: In accordance with an embodiment, a circuit includes a normally-off transistor, and a normally-on transistor comprising a second load path terminal coupled to a first load path terminal of the normally off transistor, and a control terminal coupled to a second load path terminal of the normally-off transistor. The circuit further includes a driver circuit having an output coupled to a control terminal of the normally off transistor, a first power supply terminal configured to be coupled to a first power supply terminal of a first power supply, and a second power supply terminal configured to be coupled to a second power supply terminal of a second power supply. The second load path terminal of the normally on transistor is further configured to be coupled to a second power supply terminal of the first power supply and to a first power supply terminal of the second power supply.

Abstract: In accordance with an embodiment, a circuit for driving a control terminal of a switching transistor includes a driver having an output configured to be coupled to the control terminal of the switching transistor, a first power supply terminal configured to be coupled to a first terminal of a floating power supply, a second power supply terminal configured to be coupled to a second terminal of the floating power supply, and a switching input terminal configured to receive a switching signal. The circuit further includes a bias circuit having an output terminal configured to be coupled to a common-mode control terminal of the floating power supply, wherein the bias circuit is configured to provide a time dependent voltage.

Abstract: In accordance with an embodiment, a circuit includes a first normally-on transistor having a drain coupled to a first switching output node, a normally-off transistor having a drain coupled to a source of the first normally-on transistor, a driver circuit configured to receive a switching signal, the driver circuit having an output coupled to a gate of the first normally-on transistor, and a second normally-on transistor having a drain terminal coupled to a supply node, a gate terminal coupled to the output of the driver circuit, and a source terminal configured to provide an auxiliary voltage.

Abstract: In accordance with an embodiment, a circuit includes a normally-off transistor, and a normally-on transistor comprising a second load path terminal coupled to a first load path terminal of the normally off transistor, and a control terminal coupled to a second load path terminal of the normally-off transistor. The circuit further includes a driver circuit having an output coupled to a control terminal of the normally off transistor, a first power supply terminal configured to be coupled to a first power supply terminal of a first power supply, and a second power supply terminal configured to be coupled to a second power supply terminal of a second power supply. The second load path terminal of the normally on transistor is further configured to be coupled to a second power supply terminal of the first power supply and to a first power supply terminal of the second power supply.

Abstract: In accordance with an embodiment, a circuit for driving a control terminal of a switching transistor includes a driver having an output configured to be coupled to the control terminal of the switching transistor, a first power supply terminal configured to be coupled to a first terminal of a floating power supply, a second power supply terminal configured to be coupled to a second terminal of the floating power supply, and a switching input terminal configured to receive a switching signal. The circuit further includes a bias circuit having an output terminal configured to be coupled to a common-mode control terminal of the floating power supply, wherein the bias circuit is configured to provide a time dependent voltage.

Abstract: In accordance with an embodiment, a circuit includes a first normally-on transistor having a drain coupled to a first switching output node, a normally-off transistor having a drain coupled to a source of the first normally-on transistor, a driver circuit configured to receive a switching signal, the driver circuit having an output coupled to a gate of the first normally-on transistor, and a second normally-on transistor having a drain terminal coupled to a supply node, a gate terminal coupled to the output of the driver circuit, and a source terminal configured to provide an auxiliary voltage.

Abstract: In accordance with an embodiment, a circuit includes a first driver having a first output configured to be coupled to a control node of a normally-off transistor. The first driver is configured to drive a first switching signal at the first output in a cascode mode and configured to drive a first constant voltage at the first output in a direct drive mode. The circuit further includes a second driver having a second output configured to be coupled to a control node of a normally-on transistor that has a second load path terminal coupled to a first load path terminal of the normally-off transistor. The second driver is configured to drive a second switching signal at the second output in the direct drive mode.

Abstract: In various embodiments, a switch circuit arrangement may include a switch circuit, a driver circuit and a supply circuit. The driver circuit may be configured to control the switch circuit. The supply circuit may be configured to power the driver circuit. The supply circuit may include a first circuit configured to modify an output impedance of the supply circuit to have a first impedance when the driver circuit controls the switch circuit to be in a conducting state and to have a second impedance when the driver circuit controls the switch circuit to change from a non-conducting state to the conducting state.

Abstract: In various embodiment, a switch circuit arrangement is provided. The switch circuit arrangement may include a switch circuit, a driver circuit and a supply circuit. The driver circuit may be configured to control the switch circuit. The supply circuit may be configured to power the driver circuit. The supply circuit may include a first circuit configured to modify an output impedance of the supply circuit to have a first impedance when the driver circuit controls the switch circuit to be in a conducting state and to have a second impedance when the driver circuit controls the switch circuit to change from a non-conducting state to the conducting state.