Patents by Inventor Berry Kercheval

Berry Kercheval has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 10785175
    Abstract: A messaging system in one embodiment includes a messaging app and a polling extension app. The polling extension app is configured to create data for a polling context that is displayed in a view hosted by the messaging app to allow voting by users selected for the poll and to update the polling context with the votes from the users. The messaging app launches the polling extension app, and the polling context is communicated between the polling extension app and the messaging app through an interprocess communication.
    Type: Grant
    Filed: December 22, 2016
    Date of Patent: September 22, 2020
    Assignee: Apple Inc.
    Inventors: Yik Shing Yip, Imran Chaudhri, Chanaka G. Karunamuni, Freddy Anzures, Adam P. Williams, Sami Iren, Peter Berger, Benjamin Berry Kercheval, Jr.
  • Publication number: 20170359281
    Abstract: A messaging system in one embodiment includes a messaging app and a polling extension app. The polling extension app is configured to create data for a polling context that is displayed in a view hosted by the messaging app to allow voting by users selected for the poll and to update the polling context with the votes from the users. The messaging app launches the polling extension app, and the polling context is communicated between the polling extension app and the messaging app through an interprocess communication.
    Type: Application
    Filed: December 22, 2016
    Publication date: December 14, 2017
    Inventors: Yik Shing Yip, Imran Chaudhri, Chanaka G. Karunamuni, Freddy Anzures, Adam P. Williams, Sami Iren, Peter Berger, Benjamin Berry Kercheval, JR.
  • Publication number: 20130262752
    Abstract: A multi-tiered cache manager and methods for managing multi-tiered cache are described. Multi-tiered cache manager causes cached data to be initially stored in the RAM elements and selects portions of the cached data stored in the RAM elements to be moved to the flash elements. Each flash element is organized as a plurality of write blocks having a block size and wherein a predefined maximum number of writes is permitted to each write block. The portions of the cached data may be selected based on a maximum write rate calculated from the maximum number of writes allowed for the flash device and a specified lifetime of the cache system.
    Type: Application
    Filed: February 13, 2013
    Publication date: October 3, 2013
    Inventors: Nisha Talagala, Berry Kercheval, Martin Patterson, Edward Pernicka, James Bowen
  • Patent number: 8397016
    Abstract: A multi-tiered cache manager and methods for managing multi-tiered cache are described. Multi-tiered cache manager causes cached data to be initially stored in the RAM elements and selects portions of the cached data stored in the RAM elements to be moved to the flash elements. Each flash element is organized as a plurality of write blocks having a block size and wherein a predefined maximum number of writes is permitted to each write block. The portions of the cached data may be selected based on a maximum write rate calculated from the maximum number of writes allowed for the flash device and a specified lifetime of the cache system.
    Type: Grant
    Filed: December 31, 2009
    Date of Patent: March 12, 2013
    Assignee: Violin Memory, Inc.
    Inventors: Nisha Talagala, Berry Kercheval, Martin Patterson, Edward Pernicka, James Bowen
  • Publication number: 20110145479
    Abstract: A multi-tiered cache manager and methods for managing multi-tiered cache are described. Multi-tiered cache manager causes cached data to be initially stored in the RAM elements and selects portions of the cached data stored in the RAM elements to be moved to the flash elements. Each flash element is organized as a plurality of write blocks having a block size and wherein a predefined maximum number of writes is permitted to each write block. The portions of the cached data may be selected based on a maximum write rate calculated from the maximum number of writes allowed for the flash device and a specified lifetime of the cache system.
    Type: Application
    Filed: December 31, 2009
    Publication date: June 16, 2011
    Applicant: Gear Six, Inc.
    Inventors: Nisha TALAGALA, Berry Kercheval, Martin Patterson, Edward Pernicka, James Bowen