Patents by Inventor Bert M. Vermeire
Bert M. Vermeire has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 8253422Abstract: A method of improving the clean, rinse and dry processes during the manufacture of ICs, MEMS and other micro-devices to conserve solution and energy while completing the process within a specified time. An electro-chemical residue sensor (ECRS) provides in-situ and real-time measurement of residual contamination on a surface or inside void micro features within the sensor representative of conditions on production wafers. The in-situ measurements are used to design and optimize a production process. The wafers are manufactured in accordance with the production process without the ECRS.Type: GrantFiled: March 15, 2011Date of Patent: August 28, 2012Assignee: Environmental Metrology CorporationInventors: Bert M. Vermeire, Farhang F. Shadman
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Patent number: 8120368Abstract: A method of improving the clean, rinse and dry processes during the manufacture of ICs, MEMS and other micro-devices to conserve solution and energy while completing the process within a specified time. An electro-chemical residue sensor (ECRS) provides in-situ and real-time measurement of residual contamination on a surface or inside void micro features within the sensor representative of conditions on production wafers. The measured impedance can be used to determine what process variables and specifically how process conditions affect the rate of change of the measured impedance. The in-situ measurements are used to design and optimize a production process and/or to monitor the production run in real-time to control the process conditions and transfer of a patterned wafer through the processes.Type: GrantFiled: March 14, 2011Date of Patent: February 21, 2012Assignee: Environmental Metrology CorporationInventors: Bert M. Vermeire, Farhang F. Shadman
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Patent number: 8030943Abstract: The solder-joint integrity of digital electronic packages, such as FPGAs or microcontrollers that have internally connected input/output buffers, is evaluated by applying a time-varying voltage through one or more solder-joint networks to charge a charge-storage component. Each network includes an I/O buffer on the die in the package and a solder-joint connection, typically one or more such connections inside the package and between the package and a board. The time constant for charging the component is proportional to the resistance of the solder-joint network, hence the voltage across the charge-storage component is a measurement of the integrity of the solder-joint network.Type: GrantFiled: January 26, 2009Date of Patent: October 4, 2011Assignee: Ridgetop Group, Inc.Inventors: Philipp S. Spuhler, Bert M Vermeire, James P Hofmeister
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Publication number: 20110180106Abstract: A method of improving the clean, rinse and dry processes during the manufacture of ICs, MEMS and other micro-devices to conserve solution and energy while completing the process within a specified time. An electro-chemical residue sensor (ECRS) provides in-situ and real-time measurement of residual contamination on a surface or inside void micro features within the sensor representative of conditions on production wafers. The measured impedance can be used to determine what process variables and specifically how process conditions affect the rate of change of the measured impedance. The in-situ measurements are used to design and optimize a production process and/or to monitor the production run in real-time to control the process conditions and transfer of a patterned wafer through the processes.Type: ApplicationFiled: March 15, 2011Publication date: July 28, 2011Inventors: Bert M. Vermeire, Farhang F. Shadman
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Publication number: 20110166691Abstract: A method of improving the clean, rinse and dry processes during the manufacture of ICs, MEMS and other micro-devices to conserve solution and energy while completing the process within a specified time. An electro-chemical residue sensor (ECRS) provides in-situ and real-time measurement of residual contamination on a surface or inside void micro features within the sensor representative of conditions on production wafers. The measured impedance can be used to determine what process variables and specifically how process conditions affect the rate of change of the measured impedance. The in-situ measurements are used to design and optimize a production process and/or to monitor the production run in real-time to control the process conditions and transfer of a patterned wafer through the processes.Type: ApplicationFiled: March 14, 2011Publication date: July 7, 2011Inventors: Bert M. Vermeire, Farhang F. Shadman
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Patent number: 7932726Abstract: A method of improving the clean, rinse and dry processes during the manufacture of ICs, MEMS and other micro-devices to conserve solution and energy while completing the process within a specified time. An electro-chemical residue sensor (ECRS) provides in-situ and real-time measurement of residual contamination on a surface or inside void micro features within the sensor representative of conditions on production wafers. The measured impedance can be used to determine what process variables and specifically how process conditions affect the rate of change of the measured impedance. The in-situ measurements are used to design and optimize a production process and/or to monitor the production run in real-time to control the process conditions and transfer of a patterned wafer through the processes.Type: GrantFiled: January 3, 2008Date of Patent: April 26, 2011Assignee: Environmental Metrology CorporationInventors: Bert M. Vermeire, Farhang F. Shadman
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Publication number: 20090160457Abstract: The solder-joint integrity of digital electronic packages, such as FPGAs or microcontrollers that have internally connected input/output buffers, is evaluated by applying a time-varying voltage through one or more solder-joint networks to charge a charge-storage component. Each network includes an I/O buffer on the die in the package and a solder-joint connection, typically one or more such connections inside the package and between the package and a board. The time constant for charging the component is proportional to the resistance of the solder-joint network, hence the voltage across the charge-storage component is a measurement of the integrity of the solder-joint network.Type: ApplicationFiled: January 26, 2009Publication date: June 25, 2009Applicant: RIDGETOP GROUP, INC.Inventors: Philipp S. Spuhler, Bert M. Vermeire, James P. Hofmeister
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Patent number: 7501832Abstract: The solder-joint integrity of digital electronic packages, such as FPGAs or microcontrollers that have internally connected input/output buffers, is evaluated by applying a time-varying voltage through one or more solder-joint networks to charge a charge-storage component. Each network includes an I/O buffer on the die in the package and a solder-joint connection, typically one or more such connections inside the package and between the package and a board. The time constant for charging the component is proportional to the resistance of the solder-joint network, hence the voltage across the charge-storage component is a measurement of the integrity of the solder-joint network.Type: GrantFiled: January 4, 2006Date of Patent: March 10, 2009Assignee: Ridgetop Group, Inc.Inventors: Philipp S. Spuhler, Bert M. Vermeire, James P. Hofmeister
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Patent number: 7489141Abstract: The present invention provides a micro sensor for monitoring the cleaning and drying processes of surfaces of dielectric films, micro features in porous dielectric films and biologic or other cells common in microelectronics fabrication, MEMS fabrication or microbiology test system fabrication. By embedding electrodes in the surface of a supporting dielectric, the sensor can probe the surface and pores of a covering dielectric or a cell on the covering dielectric. The addition of a guard reduces the effects of any parasitic capacitance, which extends the measurement bandwidth of the sensor and allows it to be manufactured at the scale of a single cell, a feature that is particularly important for applications in microbiology.Type: GrantFiled: August 16, 2005Date of Patent: February 10, 2009Assignee: Environmental Metrology CorporationInventors: Bert M. Vermeire, Farhang F. Shadman
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Patent number: 7332902Abstract: The present invention provides a micro sensor for monitoring the cleaning and drying processes for very high aspect ratio micro channels in dielectric films oriented parallel to the fluid-solid interface during the manufacture of ICs, MEMS and other micro-devices. The micro sensor can be used to monitor “vertical” micro features common in microelectronics fabrication or “horizontal” micro features found in MEMS or microfluidic fabrication. By forming the micro channels parallel to the interface, the channels can be made with much higher and well controlled aspect ratios. In addition, multiple sensors can sense the impedance at various points along the micro features. The addition of a guard reduces the effects of any parasitic capacitance, which extends the measurement bandwidth of the sensor.Type: GrantFiled: August 16, 2005Date of Patent: February 19, 2008Assignee: Environmental Metrology CorporationInventors: Bert M. Vermeire, Farhang F. Shadman
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Patent number: 7317317Abstract: The micro sensor is fabricated with a guard that shields the electrodes from the surrounding environment, thereby reducing loss of measurement signal through the parasitic capacitances to the substrate and fluid. The guards are low impedance points in the circuit that are biased to track as closely as possible the ac voltages of the respective electrodes. Each guard is suitably connected to the output of a guard buffer that supplies the current required to ensure that the guard is at all times at nearly the same voltage as the electrode it is guarding. The micro sensor has an improved signal to noise ratio (SNR) over an extended measurement frequency range (bandwidth) for monitoring in-situ the cleaning and drying processes for high aspect ratio micro features in dielectric films oriented perpendicular to the fluid-solid interface during the manufacture of ICs, MEMS and other micro-devices.Type: GrantFiled: August 16, 2005Date of Patent: January 8, 2008Assignee: Environmental Metrology CorporationInventors: Bert M. Vermeire, Farhang F. Shadman
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Patent number: 7271608Abstract: A prognostic cell is used to predict impending failure of a useful circuit or circuits in a host IC. Increasing the stress on the prognostic cell relative to the useful circuit shifts the failure distribution of the cell along the time axis. The relative amount of time between the useful circuit failure and prognostic cell trigger point is the “prognostic distance”. The prognostic distance is controlled by designing in the excess stress applied in test device(s), by setting the threshold for triggering in the comparison circuit or by both. Prediction accuracy is enhanced by using multiple test devices to oversample the underlying failure distribution and triggering the failure indicator when a certain fraction fail.Type: GrantFiled: November 19, 2003Date of Patent: September 18, 2007Assignee: Ridgetop Group, Inc.Inventors: Bert M. Vermeire, Harold G. Parks, Douglas L. Goodman
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Patent number: 7239163Abstract: A die-level process monitor (DLPM) provides a means for independently determining whether an IC malfunction is a result of the design or the manufacturing processing and further for gathering data on specific process parameters. The DLPM senses parameter variations that result from manufacturing process drift and outputs a measure of the process parameter. The DLPM will typically sense the mismatch of process parameters between two or more test devices as a measure of process variation between a like pair of production devices. The DLPM may be used as a diagnostic tool to determine why an IC failed to perform within specification or to gather statistics on measured process parameters for a given foundry or process.Type: GrantFiled: June 17, 2005Date of Patent: July 3, 2007Assignee: Ridgetop Group, Inc.Inventors: Jeremy John Ralston-Good, Philipp S. Spuhler, Bert M. Vermeire, Douglas Leonard Goodman
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Patent number: 7196294Abstract: A solder-joint detection circuit uses a resistive bridge and a differential detector to detect faults in the solder-joint network both inside and outside the digital electronic package during operation. The resistive bridge is preferably coupled to a high supply voltage used to power the package. Resistors R1 and R2 are connected in series at a first junction between the high and low supply voltages and a resistor R3 is coupled to the high supply voltage and connected in series with the resistance of the solder-network at a second junction. The network is held at a low voltage on the die. The detector compares the sensitivity and detection voltages and outputs a Pass/Fail signal for the solder-joint network.Type: GrantFiled: February 9, 2006Date of Patent: March 27, 2007Assignee: Ridgetop Group, Inc.Inventors: James P. Hofmeister, Philipp S. Spuhler, Bert M. Vermeire