Abstract: Implementations disclosed describe a programmable analog subsystem (PASS) having a plurality of reconfigurable analog circuits. The PASS may be coupled to an input/output device to receive an input signal and to an interface to communicate data with a central processing unit. A controller may be configured, based on a plurality of parameters stored at the controller, to configure the plurality of reconfigurable analog circuits into a first PASS state. The PASS may process the first input signal through the plurality of reconfigurable analog circuits in the first PASS state to generate a first output value based on the first input signal. Responsive to a trigger event, the controller may reconfigure the plurality of reconfigurable analog circuits into a second PASS state different from the first PASS state. The PASS may perform a function based on the first output value in the second PASS state.

Abstract: A method includes receiving a first signal, wherein the first signal is an audio signal. The method further includes providing the first signal to a first comparison circuit. The method further includes providing the first signal to a second comparison circuit. The method further includes receiving, from the first comparison circuit, a first comparison signal. The method further includes receiving, from the second comparison circuit, a second comparison signal. The method further includes providing a wake-up signal to a processing device based on the first comparison signal and the second comparison signal.

Abstract: One or more computing devices, systems, and/or methods are provided. In an example of the techniques presented herein, a method is provided. The method includes generating a bias signal based on an index, connecting a first amplifier of a first programmable analog block to a sensor terminal, and amplifying a sensor signal received at the sensor terminal in the first amplifier based on the bias signal to generate an amplified sensor signal. The amplified sensor signal is sampled to generate an output sample. Responsive to detecting a limit violation associated with the output sample, the index is modified to generate a modified index and the bias signal is adjusted based on the modified index.

Abstract: One or more computing devices, systems, and/or methods are provided. In an example of the techniques presented herein, a method is provided. The method includes generating a bias signal based on an index, connecting a first amplifier of a first programmable analog block to a sensor terminal, and amplifying a sensor signal received at the sensor terminal in the first amplifier based on the bias signal to generate an amplified sensor signal. The amplified sensor signal is sampled to generate an output sample. Responsive to detecting a limit violation associated with the output sample, the index is modified to generate a modified index and the bias signal is adjusted based on the modified index.

Abstract: One or more computing devices, systems, and/or methods are provided. In an example of the techniques presented herein, a system comprises a first input terminal and a first programmable analog block configured according to a first configuration. A controller is configured to reconfigure the first programmable analog block according to a second configuration different than the first configuration based on a first signal received at the first input terminal.

Abstract: According to some embodiments, a system comprises a memory configured to store protection waveform data, and a comparator waveform generator configured to access the memory to generate a protection waveform from the protection waveform data based on a trigger associated with the system, receive a measured system characteristic waveform, and generate a fault interrupt responsive to a comparison between the measured system characteristic waveform and the protection waveform violating a fault condition.

Abstract: Implementations disclosed describe an integrated circuit (IC) having a plurality of reconfigurable analog circuits that include a finite state machine (FSM) logic circuit and further include an interface to receive an input signal. In a first IC configuration, with the plurality of reconfigurable analog circuits having a first configuration setting, the IC may process the input signal through the plurality of reconfigurable analog circuits to generate a first output value based on the input signal. Responsive to the FSM logic circuit processing the first output value, the IC may reconfigure the plurality of reconfigurable analog circuits into a second IC configuration having a second configuration setting.

Abstract: A method includes receiving a first signal, wherein the first signal is an audio signal. The method further includes providing the first signal to a first comparison circuit. The method further includes providing the first signal to a second comparison circuit. The method further includes receiving, from the first comparison circuit, a first comparison signal. The method further includes receiving, from the second comparison circuit, a second comparison signal. The method further includes providing a wake-up signal to a processing device based on the first comparison signal and the second comparison signal.

Abstract: A method can include storing operation data in entries of memory mapped storage circuits of an integrated circuit (IC) device. The operation data of a single entry can include configuration data, an action value, and channel data having channel bits corresponding to different signal channels. Operation of the analog circuit can be configured with the configuration data. Signal channels to an analog circuit can be configured with channel data. In response to a first action value of the entry, selecting a next entry and the analog circuit and signal channels with configuration data of the next entry. In response to a second action value, ending operations of the analog circuit. Corresponding devices and systems are also disclosed.

Abstract: One or more computing devices, systems, and/or methods are provided. In an example of the techniques presented herein, a method is provided. The method includes connecting a first programmable electrode interface to one of a first working electrode, a control electrode, a reference electrode, or a guard electrode of an electrochemical cell in a first configuration, and connecting the first programmable electrode interface to a different one of the first working electrode, the control electrode, the reference electrode, or the guard electrode in a second configuration.

Abstract: One or more computing devices, systems, and/or methods are provided. In an example of the techniques presented herein, a system comprises a first input terminal and a first programmable analog block configured according to a first configuration. A controller is configured to reconfigure the first programmable analog block according to a second configuration different than the first configuration based on a first signal received at the first input terminal.

Abstract: Implementations disclosed describe a programmable analog subsystem (PASS) having a plurality of reconfigurable analog circuits. The PASS may be coupled to an input/output device to receive an input signal and to an interface to communicate data with a central processing unit. A controller may be configured, based on a plurality of parameters stored at the controller, to configure the plurality of reconfigurable analog circuits into a first PASS state. The PASS may process the first input signal through the plurality of reconfigurable analog circuits in the first PASS state to generate a first output value based on the first input signal. Responsive to a trigger event, the controller may reconfigure the plurality of reconfigurable analog circuits into a second PASS state different from the first PASS state. The PASS may perform a function based on the first output value in the second PASS state.

Abstract: Implementations disclosed describe an integrated circuit (IC) having a plurality of reconfigurable analog circuits that include a finite state machine (FSM) logic circuit and further include an interface to receive an input signal. In a first IC configuration, with the plurality of reconfigurable analog circuits having a first configuration setting, the IC may process the input signal through the plurality of reconfigurable analog circuits to generate a first output value based on the input signal. Responsive to the FSM logic circuit processing the first output value, the IC may reconfigure the plurality of reconfigurable analog circuits into a second IC configuration having a second configuration setting.

Abstract: Implementations disclosed describe a programmable analog subsystem (PASS) having a plurality of reconfigurable analog circuits. The PASS may be coupled to an input/output device to receive an input signal and to an interface to communicate data with a central processing unit. In a first PASS configuration, with the plurality of reconfigurable analog circuits having a first configuration setting, the PASS may process the input signal through the plurality of reconfigurable analog circuits to generate a first output value based on the input signal. Responsive to the first output value, the PASS may reconfigure the plurality of reconfigurable analog circuits into a second PASS configuration having a second configuration setting, such that the second configuration setting is different than the first configuration setting.

Abstract: A microcontroller comprises a plurality of digital peripheral blocks and a direct memory access (DMA) controller coupled thereto. The plurality of digital peripheral blocks includes a digital peripheral block that is configured to issue a DMA request. Upon receipt of the DMA request, the DMA controller is configured to retrieve configuration information and to write the configuration information to a configuration register associated with a circuit element of the microcontroller.

Abstract: A method for operating a system level interconnect in an integrated circuit (IC) is provided in an example embodiment. The method comprises: writing, by a microcontroller in the IC, a first configuration value into a configuration register, where the first configuration value programs the system level interconnect to couple a first peripheral to a second peripheral; monitoring the IC to determine an operational state of the IC; and in response to determining a change in the operational state of the IC, writing by the microcontroller a second configuration value into the configuration register to dynamically change interconnections in the system level interconnect between the first peripheral and the second peripheral.

Abstract: A microcontroller comprises a plurality of digital peripheral blocks and a direct memory access (DMA) controller coupled thereto. The plurality of digital peripheral blocks includes a digital peripheral block that is configured to issue a DMA request. Upon receipt of the DMA request, the DMA controller is configured to retrieve configuration information and to write the configuration information to a configuration register associated with a circuit element of the microcontroller.

Abstract: A method for operating a system level interconnect in an integrated circuit (IC) is provided in an example embodiment. The method comprises: writing, by a microcontroller in the IC, a first configuration value into a configuration register, where the first configuration value programs the system level interconnect to couple a first peripheral to a second peripheral; monitoring the IC to determine an operational state of the IC; and in response to determining a change in the operational state of the IC, writing by the microcontroller a second configuration value into the configuration register to dynamically change interconnections in the system level interconnect between the first peripheral and the second peripheral.

Abstract: A programmable device comprises a plurality of programmable blocks, a debug interface coupled with the plurality of programmable blocks, a debug interface coupled with the plurality of programmable blocks, and a power manger coupled with the plurality of programmable blocks. The power manager is configured to supply power to a subset of the plurality of programmable blocks during debugging of the subset while maintaining a different subset of the plurality of programmable blocks in a lower power mode.

Abstract: Implementations disclosed describe a programmable analog subsystem (PASS) having a plurality of reconfigurable analog circuits. The PASS may be coupled to an input/output device to receive an input signal and to an interface to communicate data with a central processing unit. In a first PASS configuration, with the plurality of reconfigurable analog circuits having a first configuration setting, the PASS may process the input signal through the plurality of reconfigurable analog circuits to generate a first output value based on the input signal. Responsive to the first output value, the PASS may reconfigure the plurality of reconfigurable analog circuits into a second PASS configuration having a second configuration setting, such that the second configuration setting is different than the first configuration setting.