Abstract: A temperature sensing circuit is described providing a low power temperature sensing system. The temperature sensing circuit provides a digital method for determining the temperature by analyzing the change in electrical response characteristics of a circuit device.

Abstract: The present disclosure includes a power measurement, circuit breaker or integrated protection system including isolated analog-to-digital modulators for measuring current using current sensors, such as, for example, current shunts, in a single or multiphase power system. In one embodiment, the modulators are divided into a line-side device with an analog-to-digital modulator and a host-side device including a decimation filter and a processor. In one embodiment, an isolation barrier, such as, for example, a pulse transformer, divides the lineside device from the host-side device.

Abstract: The present disclosure includes a power measurement, circuit breaker or integrated protection system including isolated analog-to-digital modulators for measuring current using current sensors, such as, for example, current shunts, in a single or multiphase power system. In one embodiment, the modulators are divided into a line-side device with an analog-to-digital modulator and a host-side device including a decimation filter and a processor. In one embodiment, an isolation barrier, such as, for example, a pulse transformer, divides the line-side device from the host-side device.

Abstract: A temperature sensing circuit is described providing a low power temperature sensing system. The temperature sensing circuit provides a digital method for determining the temperature by analyzing the change in electrical response characteristics of a circuit device.

Abstract: The present disclosure includes a power measurement, circuit breaker or integrated protection system including isolated analog-to-digital modulators for measuring current using current sensors, such as, for example, current shunts, in a single or multiphase power system. In one embodiment, the modulators are divided into a line-side device with an analog-to-digital modulator and a host-side device including a decimation filter and a processor. In one embodiment, an isolation barrier, such as, for example, a pulse transformer, divides the line-side device from the host-side device.

Abstract: The present disclosure includes a power measurement, circuit breaker or integrated protection system including isolated analog-to-digital modulators for measuring current using current sensors, such as, for example, current shunts, in a single or multiphase power system. In one embodiment, the modulators are divided into a line-side device with an analog-to-digital modulator and a host-side device including a decimation filter and a processor. In one embodiment, an isolation barrier, such as, for example, a pulse transformer, divides the line-side device from the host-side device.

Abstract: A method and apparatus for obtaining power computation parameters is presented. Accurate computation of power requires multiplying voltage and current at the same instant of time and integrating the results over time. The present invention provides a method of using a single Analog to Digital Converter to convert both voltage and current for all the phases of any electrical system and then digitally compensating for the phase error caused by the non-simultaneous sampling of the current and voltage signals. The compensating filter could be implemented as a simple interpolator, an all-pass filter, or a combination of both. A single multiplexer is used to select which signal is processed by the Analog to Digital Converter. By scheduling and converting the voltage and analog signals one at a time, potential for crosstalk is significantly reduced, power requirement is reduced, and die size requirement is reduced.

Abstract: A method and apparatus for obtaining power computation parameters is presented. Accurate computation of power requires multiplying voltage and current at the same instant of time and integrating the results over time. The present invention provides a method of using a single Analog to Digital Converter to convert both voltage and current for all the phases of any electrical system and then digitally compensating for the phase error caused by the non-simultaneous sampling of the current and voltage signals. The compensating filter could be implemented as a simple interpolator, an all-pass filter, or a combination of both. A single multiplexer is used to select which signal is processed by the Analog to Digital Converter. By scheduling and converting the voltage and analog signals one at a time, potential for crosstalk is significantly reduced, power requirement is reduced, and die size requirement is reduced.

Abstract: A method and apparatus for obtaining power computation parameters is presented. Accurate computation of power requires multiplying voltage and current at the same instant of time and integrating the results over time. The present invention provides a method of using a single Analog to Digital Converter to convert both voltage and current for all the phases of any electrical system and then digitally compensating for the phase error caused by the non-simultaneous sampling of the current and voltage signals. The compensating filter could be implemented as a simple interpolator, an all-pass filter, or a combination of both. A single multiplexer is used to select which signal is processed by the Analog to Digital Converter. By scheduling and converting the voltage and analog signals one at a time, potential for crosstalk is significantly reduced, power requirement is reduced, and die size requirement is reduced.

Abstract: A method and apparatus for obtaining power computation parameters is presented. Accurate computation of power requires multiplying voltage and current at the same instant of time and integrating the results over time. The present invention provides a method of using a single Analog to Digital Converter to convert both voltage and current for all the phases of any electrical system and then digitally compensating for the phase error caused by the non-simultaneous sampling of the current and voltage signals. The compensating filter could be implemented as a simple interpolator, an all-pass filter, or a combination of both. A single multiplexer is used to select which signal is processed by the Analog to Digital Converter. By scheduling and converting the voltage and analog signals one at a time, potential for crosstalk is significantly reduced, power requirement is reduced, and die size requirement is reduced.

Abstract: A method and circuit are presented for operating a polyphase dc motor in which drive voltages are applied to the windings of the motor in predetermined phases. Zero crossings of currents flowing in respective windings of the motor are detected, and phases of the drive voltages are adjusted to have zero crossings substantially simultaneously with the detected zero crossings of the currents flowing in respective windings of the motor. The method includes generating a set of three waveforms (45,46,47) to provide drive voltages to respective windings of the motor. Each waveform has a period of 360° with a first segment (43) having a value of zero for 120°, followed by a second segment (50) having an “up slope” shape for 60°, followed by a third segment (67,68) having two consecutive “cap” shapes for 120°, followed by a fourth segment (52) having “down slope” shape for 60°. Each waveform of said set is displaced from one another by 120°.

Abstract: The present invention discloses a circuit to reduce current and voltage spikes when switching inductive loads. The circuit of the present invention achieves this reduction in voltage and current spikes without requiring the prior art's large sizes for the transistors driving the inductive load. The invention results in reduced cost and power consumption. Moreover, the invention's circuit maintains a fast switching time for the transistors driving the inductive load. The invention's circuit comprises a current steering mechanism which directs current to one of the two drivers driving an inductive load. According to the invention, current is directed to the driver coupled to the supply voltage, the driver coupled to ground, or both in different amounts. The current is directed to the drivers such that the effect of flyback voltage caused by switching the inductive load is reduced.

Abstract: A precision resistor using MOS devices. The present invention utilizes an NMOS resistive element to simulate the resistor. A pair of PMOS source followers are implemented to control the value of the resistor and cancel the non-linearity due to the drain-source voltage V.sub.ds. A pair of NMOS source followers serve to eliminate non-linear distortions due to the "body effect" that can exist in the resistive element. The resistor circuit of the present invention provides higher precision, linearity and high value resistors in a smaller area than prior art MOS resistors.

Abstract: The switched capacitor amplifier circuit of the present invention employs a single amplifier with a built-in sample and hold and input auto zero. The built-in sample and hold of the present invention provides a continuously valid output in a multi-phase system. The present invention comprises a new auto zero configuration and a new amplifier. The new amplifier is referred to as the AZAMP. The circuit configuration of the AZAMP of the present invention comprises a two stage amplifier with switches added to the circuitry to provide the sample and hold function. By disconnecting the second stage during the hold mode, the output voltage will remain unchanged due to the voltage stored on a capacitor within the AZAMP. Charge cancelling circuitry is coupled to the sample and hold circuitry to cancel the charge injected onto said capacitor when the switch is turned off. The AZAMP of the present invention also has a self-contained auto zero function.

Abstract: A secondary channel FSK modem for use with primary channel QAM modems is described. The present invention is a fully integrated 75 bps narrowband secondary channel FSK modem which may be utilized with a primary channel QAM modem at data rates up to 19.2 kbps. The present invention applies switched capacitor circuits to implement band split filters and FSK transmitters. A micro-digital signal processor is implemented to realize the FSK receiver to achieve higher performance, long-term stability and versatility. The present invention provides 40 Hz separation of two carrier frequencies to improve bandwidth efficiency. In operation, an FSK modulator is combined with a highpass filter and delay equalizer to separate a section of the main channel bandwidth for use with the secondary channel. The FSK signal and QAM signal are then summed and provided to a smoothing filter for transmission line output.

Abstract: The switched-capacitor differential amplifier circuit of the present invention employs a more efficient switched-capacitor network to provide a common mode range which is not limited by the amplifier power supply, and to achieve a high common mode rejection ratio at high frequencies with decreased sensitivity to component tolerances. The circuit employs a two-phase system, during the first phase of which, the circuit is auto-zeroed, the differential inputs are sampled and the capacitors are pre-charged. During the second phase, the differential inputs are disconnected and the bottom plates of the input capacitors are coupled together. The charge redistribution within the circuit forms an output potential that is proportional to the difference between the input signals, and that is offset by a user specified voltage. The present invention substantially eliminates the effects of parasitic capacitance.

Abstract: A method and apparatus for removing the effects of mismatched components in an A/D converter is described. The present invention dynamically rearranges the capacitors of an A/D converter so that physical mismatch is averaged out. In the preferred embodiment of the present invention, an array of equally-sized capacitors is coupled to a switching network. A successive approximation scheme is implemented in which the input signal is coupled through SAR switches to the capacitor array. Each switch is coupled to 2.sup.N-1 capacitors where N is the switch number. For example, in an 8-bit scheme, there are 3 switches with switch 1 coupled to one capacitor, switch 2 coupled to two capacitors, and switch 3 coupled to four capacitors. In this manner, eight levels of capacitance values can be defined. The present invention adds a scramble control code to control the switching array so that the physical capacitors themselves are coupled to different SAR switches at different times.