Abstract: Techniques, apparatuses, and systems for interfacing multiple sensors with a biological system can include amplifying signals from respective sensors associated with an external device; modulating the amplified signals based on respective different frequency values; and summing the modulated signals to produce an output signal to stimulate a biological system.

Abstract: Systems and methods are provided for monitoring a voltage. A level shifter is configured to generate a current proportional to the voltage of the battery cell. A delta-sigma modulator is configured to convert the current into a first density modulated bitstream representing the voltage of the battery cell. A first reference source is configured to provide a second density modulated bitstream representing a first threshold voltage. A first comparator is configured to compare the first density modulated bitstream and the second density modulated bitstream.

Abstract: A closed-loop controlled antenna tuning unit (ATU) system includes a return loss detector connected to sample an RF signal generated by a signal source to provide a return loss signal. A matching state searching circuit is connected to receive the return loss signal and, in response, selectively store a return loss value and an impedance matching state. A central controller is connected to provide a switch control signal and apply an optimum matching state to the impedance synthesizer at the conclusion of the matching state search. An impedance synthesizer is responsive to the switch control signal for coupling a radio frequency signal and matching the impedance of an antenna to a signal source.

Abstract: A relatively low frequency chopping operation is applied to a delta-sigma ADC to reduce DC offsets resulting from non-ideal component operation. Sequential chopping takes place outside a closed loop and may include an inverted polarity feedback for a part of the chopping period. Nested chopping involves chopping within the closed loop, and may include an inverted polarity feedback and a time shift. The feedback compensation for sequential and nested chopping permits the correct polarity feedback to be provided at the desired time in conjunction with sampling and quantization events. Integrating capacitor(s) may be swapped in relative polarity during nested chopping to preserve residual conversion information for the desired polarity. The ADC operation is non-temperature dependent and avoids modification to the useful signal, resulting in higher accuracy.

Abstract: A relatively low frequency chopping operation is applied to a delta-sigma ADC to reduce DC offsets resulting from non-ideal component operation. Sequential chopping takes place outside a closed loop and may include an inverted polarity feedback for a part of the chopping period. Nested chopping involves chopping within the closed loop, and may include an inverted polarity feedback and a time shift. The feedback compensation for sequential and nested chopping permits the correct polarity feedback to be provided at the desired time in conjunction with sampling and quantization events. Integrating capacitor(s) may be swapped in relative polarity during nested chopping to preserve residual conversion information for the desired polarity. The ADC operation is non-temperature dependent and avoids modification to the useful signal, resulting in higher accuracy.

Abstract: A noise-shaped direct digital IF to RF DAC (DIF2RF) with embedded up-converter mixer is presented. The digital IF signal is noised shaped by a band-pass ?? modulator with a single bit IF output followed by a semi-digital current-mode IF filter to attenuate out-of-band quantization noise. A current steering DAC combines scaled values of local oscillator (LO) signals as current sources for performing current steering and upconversion in a single cell.

Abstract: A closed-loop controlled antenna tuning unit (ATU) system includes a return loss detector connected to sample an RF signal generated by a signal source to provide a return loss signal. A matching state searching circuit is connected to receive the return loss signal and, in response, selectively store a return loss value and an impedance matching state. A central controller is connected to provide a switch control signal and apply an optimum matching state to the impedance synthesizer at the conclusion of the matching state search. An impedance synthesizer is responsive to the switch control signal for coupling a radio frequency signal and matching the impedance of an antenna to a signal source.

Abstract: Low noise, low dropout regulators are described. An example low noise, low dropout regulator includes a chopping error amplifier to receive an input signal and a feedback signal and to output a modified signal having an undesired portion of the input signal shifted to a higher frequency and a regulator to receive the modified signal and to generate an output signal by filtering the undesired portion of the input signal from the modified signal.

Abstract: A sample-and-hold (SAH) phase detector (PD) is clocked in such a way (using a reverse clocking mode) so as to avoid quantization noise increases due to folding that is generally associated with conventional charge pump based phase detectors. The PD is clocked with a clean clock (reference clock), rather than a divided clock. The SAH PD architecture additionally includes an integrated filtering function.

Abstract: A latch architecture for driving unit current cell of a current-steering digital-to-analog converter (DAC) which reduces the drain-source voltage variation of the output current-source transistors and reduces the coupling of unwanted injection of input digital signals as well as clock signals is presented herein. Moreover, this latch helps to achieve lower glitch during code transition with improved dynamic performance. The latch effectively uses the intrinsic RC delay of most transistors within the latch architecture in order to achieve optimal crossing points of complementary control signals. Unwanted input injection or cross-talk is reduced by introducing transistors (904, 906, 932 and 934) that are off during code transitions without compromising the DAC update speed. Conflicts between currently held and new inputs are avoided in an effort to reduce the harmonic distortion.

Abstract: A latch architecture for driving unit current cell of a current-steering digital-to-analog converter (DAC) which reduces the drain-source voltage variation of the output current-source transistors and reduces the coupling of unwanted injection of input digital signals as well as clock signals is presented herein. Moreover, this latch helps to achieve lower glitch during code transition with improved dynamic performance. The latch effectively uses the intrinsic RC delay of most transistors within the latch architecture in order to achieve optimal crossing points of complementary control signals. Unwanted input injection or cross-talk is reduced by introducing transistors (904, 906, 932 and 934) that are off during code transitions without compromising the DAC update speed. Conflicts between currently held and new inputs are avoided in an effort to reduce the harmonic distortion.

Abstract: A technique is provided for achieving efficient modulation compensation of a &Sgr;&Dgr; fractional PLL. The parameters of the PLL TF are the gain, Kpll, of the PLL and the time constants associated with the loop filter. A careful design of the PLL allows setting the poles and zeros of the PLL TF to fixed values, independent of process and temperature. The unknown parameters of the system are then reduced to one: the PLL gain, K which is the product of the Voltage Controlled Oscillator (VCO), Phase Detector (PD) and divider gains. One unknown variable can be then determined via a single equation, that can be derived at a single frequency. The measurement of a low frequency modulated single tone, for example, is sufficient to characterize the entire PLL TF.

Abstract: A sample-and-hold (SAH) phase detector (PD) is clocked in such a way (using a reverse clocking mode) so as to avoid quantization noise increases due to folding that is generally associated with conventional charge pump based phase detectors. The PD is clocked with a clean clock (reference clock), rather than a divided clock. The SAH PD architecture additionally includes an integrated filtering function.

Abstract: A technique is provided for achieving efficient modulation compensation of a &Sgr;&Dgr; fractional PLL. The parameters of the PLL TF are the gain, Kpll, of the PLL and the time constants associated with the loop filter. A careful design of the PLL allows setting the poles and zeros of the PLL TF to fixed values, independent of process and temperature. The unknown parameters of the system are then reduced to one: the PLL gain, K which is the product of the Voltage Controlled Oscillator (VCO), Phase Detector (PD) and divider gains. One unknown variable can be then determined via a single equation, that can be derived at a single frequency. The measurement of a low frequency modulated single tone, for example, is sufficient to characterize the entire PLL TF.