Abstract: A serial buffer includes queues configured to store data packets received from a host. A direct memory access (DMA) engine receives data packets from the highest priority queue having a water level that reaches a corresponding watermark. The DMA engine is configured in response to a DMA register set, which is selected from a plurality of DMA register sets. The DMA register set used to configure the DMA engine can be selected in response to information in the header of the read data packet, or in response to the queue from which the data packet is read. Each DMA register set defines a corresponding buffer in system memory, to which the data packet is transferred. Each DMA register set also defines whether the corresponding buffer is accessed in a wrap mode or a stop mode, and whether doorbell signals are generated in response to transfers to the last address in the corresponding buffer.

Abstract: A serial buffer monitors an incoming stream of packets to identify single missing packets and multiple consecutive missing packets. Upon detecting multiple consecutive missing packets, an interrupt is generated, thereby stopping the data transfer. Upon detecting a single missing packet, a single missing packet identifier is inserted into the packet header of the packet that resulted in identification of the single missing packet. The incoming packets, including any inserted single missing packet identifiers, are written to a queue. When the water level reaches the water mark of the queue, the stored packets are read to create an outgoing packet stream. When a packet read from the queue includes an inserted single missing packet identifier, a dummy packet (e.g., a packet having a data payload of all zeros) is inserted into the outgoing packet stream. As a result, real-time applications are capable of processing the outgoing packet stream in a constant fashion.

Abstract: A packet switching integrated circuit chip is configured to receive packets, e.g., RapidIO™-compliant packets, from a plurality of external sources, and selectively passes data in the received packets to a plurality of external recipients. The chip is configured to pass first received packets without modification and to terminate second received packets and preprocess payloads thereof to produce new packets. The chip may be configured to perform signal sample processing operations on the second received packets, such as bit extension, bit truncation, bit reordering and/or bit arithmetic operations. The chip may be further configured to manage the first and second received packets based on destination addresses in the received packets.

Abstract: A serial buffer is configured to transmit a plurality of received data packets through a data packet transfer path to a host processor. A doorbell controller of the serial buffer monitors the number of data packets transmitted to the host processor through the data packet transfer path, and estimates the number of data packets actually received by the host processor. The doorbell controller generates a doorbell command each time that the estimated number of data packets corresponds with a fixed number of data packets in a frame. The doorbell commands are transmitted to the host processor on a doorbell command path, which is faster than the data packet transfer path. The doorbell controller may estimate the number of data packets actually received by the host processor in response to a first delay value, which represents how much faster the doorbell command path is than the data packet transfer path.

Abstract: A packet processing integrated circuit chip includes a plurality of input ports configured to receive packets from respective external sources and a plurality of output ports configured to transmit packets to respective external recipients. The chip further includes a packet processor configurable to extract data from payloads of the received packets, to process the extracted data to produce new packets with payloads having formats compatible with data structures of the external recipients, and to convey the new packets to the output ports. The chip may further include a packet switching fabric configured to route selected packets from the input ports to selected ones of the output ports without payload modification.

Abstract: A baseband processor includes a processing switch for performing orthogonal frequency division multiplexing operations on data packets and routing the data packets in the baseband processor. Additionally, the baseband processor includes digital signal processors for performing symbol processing operations on the data packets. The baseband processor is scalable such that digital signal processors may be added to, or removed from, the baseband processor. Further, the baseband processor is programmable such that the symbol processing operations may be distributed among the digital signal processors.

Abstract: A serial buffer monitors an incoming stream of packets to identify single missing packets and multiple consecutive missing packets. Upon detecting multiple consecutive missing packets, an interrupt is generated, thereby stopping the data transfer. Upon detecting a single missing packet, a single missing packet identifier is inserted into the packet header of the packet that resulted in identification of the single missing packet. The incoming packets, including any inserted single missing packet identifiers, are written to a queue. When the water level reaches the water mark of the queue, the stored packets are read to create an outgoing packet stream. When a packet read from the queue includes an inserted single missing packet identifier, a dummy packet (e.g., a packet having a data payload of all zeros) is inserted into the outgoing packet stream. As a result, real-time applications are capable of processing the outgoing packet stream in a constant fashion.

Abstract: A serial buffer is configured to transmit a plurality of received data packets through a data packet transfer path to a host processor. A doorbell controller of the serial buffer monitors the number of data packets transmitted to the host processor through the data packet transfer path, and estimates the number of data packets actually received by the host processor. The doorbell controller generates a doorbell command each time that the estimated number of data packets corresponds with a fixed number of data packets in a frame. The doorbell commands are transmitted to the host processor on a doorbell command path, which is faster than the data packet transfer path. The doorbell controller may estimate the number of data packets actually received by the host processor in response to a first delay value, which represents how much faster the doorbell command path is than the data packet transfer path.

Abstract: A serial buffer includes queues configured to store data packets received from a host. A direct memory access (DMA) engine receives data packets from the highest priority queue having a water level that reaches a corresponding watermark. The DMA engine is configured in response to a DMA register set, which is selected from a plurality of DMA register sets. The DMA register set used to configure the DMA engine can be selected in response to information in the header of the read data packet, or in response to the queue from which the data packet is read. Each DMA register set defines a corresponding buffer in system memory, to which the data packet is transferred. Each DMA register set also defines whether the corresponding buffer is accessed in a wrap mode or a stop mode, and whether doorbell signals are generated in response to transfers to the last address in the corresponding buffer.

Abstract: A packet processing integrated circuit chip includes a plurality of input ports configured to receive packets from respective external sources and a plurality of output ports configured to transmit packets to respective external recipients. The chip further includes a packet processor configurable to extract data from payloads of the received packets, to process the extracted data to produce new packets with payloads having formats compatible with data structures of the external recipients, and to convey the new packets to the output ports. The chip may further include a packet switching fabric configured to route selected packets from the input ports to selected ones of the output ports without payload modification.

Abstract: A packet processing integrated circuit chip includes a plurality of input ports configured to receive packets from respective external sources and a plurality of output ports configured to transmit packets to respective external recipients. The chip further includes a packet processor configured to process the received packets to generate new packets with new payloads according to selected ones of a plurality of packet processing scenarios based on destination addresses in the received packets. The plurality of packet processing scenarios may include individual packet processing scenarios and group packet processing scenarios that invoke parallel processing of a packet by selected ones of the individual packet processing scenarios. The chip may further include a packet switching fabric configured to route selected packets from the input ports to selected ones of the output ports without payload modification.

Abstract: A packet switching integrated circuit chip is configured to receive packets, e.g., RapidIO™-compliant packets, from a plurality of external sources, and selectively passes data in the received packets to a plurality of external recipients. The chip is configured to pass first received packets without modification and to terminate second received packets and preprocess payloads thereof to produce new packets. The chip may be configured to perform signal sample processing operations on the second received packets, such as bit extension, bit truncation, bit reordering and/or bit arithmetic operations. The chip may be further configured to manage the first and second received packets based on destination addresses in the received packets.

Abstract: A CAM array block is configured to perform a search operation in a staged segment-to-segment manner using a plurality of hybrid comparands that are pipelined into the CAM array block during consecutive stages of the search operation. These hybrid comparands include at least a virtual sector field and a data field. The CAM array block is also responsive to a segment address, which identifies an active segment of CAM cells in said CAM array block. The CAM array block may include a CAM array and a global mask cell sub-array that is electrically coupled to the CAM array. This global mask cell sub-array may be responsive to the segment address and a mode select signal. A bit/data line control circuit is also provided. The bit/data line control circuit is electrically coupled to the CAM array by bit lines and data lines and has inputs that are responsive to signals generated by the global mask cell sub-array. The device may also include an address translation unit that is responsive to an input address.

Abstract: CAM devices and methods of operating CAM devices include mapping search word portions to partitions and virtual subpartitions in a CAM core. Some embodiments of the invention can provide, for example, a hybrid CAM device that includes a mapping circuit for implementing such partitioning and virtual subpartitioning that is implemented in memory, such as a random access memory (RAM) or a combination of CAM and RAM, that is integrated with the CAM core. In some embodiments, a CAM device includes a search word input, a CAM core comprising a plurality of CAM cells, and a virtual partitioning circuit that selectively enables a partition in the CAM core for search of a portion of a search word at the search word input responsive to the search word, and that provides a mapping of the search word to a comparand input to the CAM core. The mapping defines a virtual subpartition in the CAM core. The invention may be embodied as apparatus and methods.

Abstract: A system and method for encoding and decoding data utilizes Walsh-Hadamard Transforms and inversion techniques to generate the possible minimum disparity values for the data to be encoded. A minimum disparity value is then selected that also provides sufficient transition density.