Patents by Inventor Berthold Schuderer
Berthold Schuderer has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 9312226Abstract: A semiconductor device includes a chip, a contact pad arranged over the front side of the chip and an identification mark arranged over the contact pad. The identification mark includes an information about a property of the chip.Type: GrantFiled: December 14, 2012Date of Patent: April 12, 2016Assignee: Infineon Technologies AGInventors: Stefan Martens, Berthold Schuderer, Mathias Vaupel, Raimund Peichl
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Publication number: 20160086842Abstract: A method for producing a semiconductor device having a sidewall insulation includes providing a semiconductor body having a first side and a second side lying opposite the first side. At least one first trench is at least partly filled with insulation material proceeding from the first side in the direction toward the second side into the semiconductor body. The at least one first trench is produced between a first semiconductor body region for a first semiconductor device and a second semiconductor body region for a second semiconductor device. An isolating trench extends from the first side of the semiconductor body in the direction toward the second side of the semiconductor body between the first and second semiconductor body regions in such a way that at least part of the insulation material of the first trench adjoins at least a sidewall of the isolating trench. The second side of the semiconductor body is partly removed as far as the isolating trench.Type: ApplicationFiled: December 1, 2015Publication date: March 24, 2016Inventors: CARSTEN AHRENS, RUDOLF BERGER, MANFRED FRANK, UWE HOECKELE, BERNHARD KNOTT, ULRICH KRUMBEIN, WOLFGANG LEHNERT, BERTHOLD SCHUDERER, JUERGEN WAGNER, STEFAN WILLKOFER
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Patent number: 9236290Abstract: A method for producing a semiconductor device having a sidewall insulation includes providing a semiconductor body having a first side and a second side lying opposite the first side. At least one first trench is at least partly filled with insulation material proceeding from the first side in the direction toward the second side into the semiconductor body. The at least one first trench is produced between a first semiconductor body region for a first semiconductor device and a second semiconductor body region for a second semiconductor device. An isolating trench extends from the first side of the semiconductor body in the direction toward the second side of the semiconductor body between the first and second semiconductor body regions in such a way that at least part of the insulation material of the first trench adjoins at least a sidewall of the isolating trench. The second side of the semiconductor body is partly removed as far as the isolating trench.Type: GrantFiled: February 3, 2012Date of Patent: January 12, 2016Assignee: Infineon Technologies AGInventors: Carsten Ahrens, Rudolf Berger, Manfred Frank, Uwe Hoeckele, Bernhard Knott, Ulrich Krumbein, Wolfgang Lehnert, Berthold Schuderer, Juergen Wagner, Stefan Willkofer
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Publication number: 20140167272Abstract: A semiconductor device includes a chip, a contact pad arranged over the front side of the chip and an identification mark arranged over the contact pad. The identification mark includes an information about a property of the chip.Type: ApplicationFiled: December 14, 2012Publication date: June 19, 2014Applicant: INFINEON TECHNOLOGIES AGInventors: Stefan Martens, Berthold Schuderer, Mathias Vaupel, Raimund Peichl
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Patent number: 8753982Abstract: A method for producing a connection region on a side wall of a semiconductor body is disclosed. A first trench is produced on a first surface of a semiconductor body and extends into the semiconductor body. An insulation layer is formed on the side walls and on the bottom of the first trench, and the first trench is only partially filled. The unfilled part of the first trench is filled with an electrically conductive material. A separating trench is produced along the first trench in such a way that a side wall of the separating trench directly adjoins the first trench. The part of the insulation layer which adjoins the separating trench is at least partially removed, with the result that at least some of the electrically conductive material in the first trench is exposed.Type: GrantFiled: May 10, 2012Date of Patent: June 17, 2014Assignee: Infineon Technologies AGInventors: Carsten Ahrens, Berthold Schuderer, Stefan Willkofer
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Patent number: 8637967Abstract: A method includes structuring a semiconductor substrate to produce a number semiconductor chips. Each of the semiconductor chips includes a first main face and a number of side faces. An indentation is formed at a transition between the first main face and the side faces.Type: GrantFiled: November 15, 2010Date of Patent: January 28, 2014Assignee: Infineon Technologies AGInventors: Markus Menath, Hermann Wendt, Berthold Schuderer
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Publication number: 20120289023Abstract: A method for producing a semiconductor device having a sidewall insulation includes providing a semiconductor body having a first side and a second side lying opposite the first side. At least one first trench is at least partly filled with insulation material proceeding from the first side in the direction toward the second side into the semiconductor body. The at least one first trench is produced between a first semiconductor body region for a first semiconductor device and a second semiconductor body region for a second semiconductor device. An isolating trench extends from the first side of the semiconductor body in the direction toward the second side of the semiconductor body between the first and second semiconductor body regions in such a way that at least part of the insulation material of the first trench adjoins at least a sidewall of the isolating trench. The second side of the semiconductor body is partly removed as far as the isolating trench.Type: ApplicationFiled: February 3, 2012Publication date: November 15, 2012Applicant: INFINEON TECHNOLOGIES AGInventors: Carsten Ahrens, Rudolf Berger, Manfred Frank, Uwe Hoeckele, Bernhard Knott, Ulrich Krumbein, Wolfgang Lehnert, Berthold Schuderer, Juergen Wagner, Stefan Willkofer
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Publication number: 20120289047Abstract: A method for producing a connection region on a side wall of a semiconductor body is disclosed. A first trench is produced on a first surface of a semiconductor body and extends into the semiconductor body. An insulation layer is formed on the side walls and on the bottom of the first trench, and the first trench is only partially filled. The unfilled part of the first trench is filled with an electrically conductive material. A separating trench is produced along the first trench in such a way that a side wall of the separating trench directly adjoins the first trench. The part of the insulation layer which adjoins the separating trench is at least partially removed, with the result that at least some of the electrically conductive material in the first trench is exposed.Type: ApplicationFiled: May 10, 2012Publication date: November 15, 2012Applicant: INFINEON TECHNOLOGIES AGInventors: Carsten Ahrens, Berthold Schuderer, Stefan Willkofer
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Publication number: 20120119389Abstract: A method includes structuring a semiconductor substrate to produce a number semiconductor chips. Each of the semiconductor chips includes a first main face and a number of side faces. An indentation is formed at a transition between the first main face and the side faces.Type: ApplicationFiled: November 15, 2010Publication date: May 17, 2012Inventors: Markus Menath, Hermann Wendt, Berthold Schuderer
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Patent number: 8163629Abstract: In one embodiment, a method for forming the semiconductor device includes forming a first trench from a front side of a substrate. The substrate has a front side and an opposite back side, and the first trench having sidewalls and a bottom surface. A insulator layer is formed over the sidewalls and the bottom surface. A first conductive layer is formed over a top portion of the sidewalls of the first trench. The substrate is separated along the first trench.Type: GrantFiled: August 5, 2010Date of Patent: April 24, 2012Assignee: Infineon Technologies AGInventors: Berthold Schuderer, Carsten Ahrens
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Publication number: 20120034760Abstract: In one embodiment, a method for forming the semiconductor device includes forming a first trench from a front side of a substrate. The substrate has a front side and an opposite back side, and the first trench having sidewalls and a bottom surface. A insulator layer is formed over the sidewalls and the bottom surface. A first conductive layer is formed over a top portion of the sidewalls of the first trench. The substrate is separated along the first trench.Type: ApplicationFiled: August 5, 2010Publication date: February 9, 2012Inventors: Berthold Schuderer, Carsten Ahrens
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Patent number: 7825510Abstract: A method in which a base layer is deposited in a contact hole region under a protective gas, where base layer contains a nitride as main constituent. After the deposition of the base layer, a covering layer is deposited under gaseous nitrogen. An adhesion promoting layer results which is simple to produce and has good electrical properties.Type: GrantFiled: February 15, 2008Date of Patent: November 2, 2010Assignee: Infineon Technologies AGInventors: Jürgen Förster, Klemens Prügl, Berthold Schuderer
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Patent number: 7816791Abstract: A bonding pad on a substrate has a first metal structure establishing an electrical connection between a device and a bonding area, and a second metal structure arranged at the bonding area. The first metal structure extends, within the bonding area, at least over part of the bonding area between the substrate and the second metal structure, so as to contact the second metal structure, the second metal structure being harder than the first metal structure.Type: GrantFiled: September 12, 2007Date of Patent: October 19, 2010Assignee: Infineon Technologies AGInventors: Carsten Ahrens, Sven Albers, Klaus Gnannt, Ulrich Krumbein, Gunther Mackh, Patrick Schelauske, Berthold Schuderer, Georg Seidemann
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Patent number: 7660175Abstract: An embodiment of an integrated circuit comprises a plurality of cells. Each cell comprises a first supply node, a second supply node, a series connection with a first transistor, a second transistor and an electrical element. The series connection is coupled between the first and the second supply node. The electrical element includes a first and a second node. A third transistor is coupled between the first node of the electrical element and a first output node of the cell and a fourth transistor is coupled between the second node of the electrical element and the second output node of the cell. A control terminal of the first, the third and the fourth transistor is coupled to a first control node of the cell and a control terminal of the second transistor is coupled to a second control node of the cell.Type: GrantFiled: February 29, 2008Date of Patent: February 9, 2010Assignee: Infineon Technologies AGInventors: Dieter Kohlert, Erhard Sixt, Rainer Holmer, Georg Seidemann, Berthold Schuderer, Gunther Mackh, Sabine Penka, Grit Schwalbe-Dietrich, Bernhard Duschinger, Josef Hermann
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Publication number: 20090219773Abstract: An embodiment of an integrated circuit comprises a plurality of cells. Each cell comprises a first supply node, a second supply node, a series connection with a first transistor, a second transistor and an electrical element. The series connection is coupled between the first and the second supply node. The electrical element includes a first and a second node. A third transistor is coupled between the first node of the electrical element and a first output node of the cell and a fourth transistor is coupled between the second node of the electrical element and the second output node of the cell. A control terminal of the first, the third and the fourth transistor is coupled to a first control node of the cell and a control terminal of the second transistor is coupled to a second control node of the cell.Type: ApplicationFiled: February 29, 2008Publication date: September 3, 2009Inventors: Dieter Kohlert, Erhard Sixt, Rainer Holmer, Georg Seidemann, Berthold Schuderer, Gunther Mackh, Sabine Penka, Grit Schwalbe-Dietrich, Bernhard Duschinger, Josef Hermann
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Patent number: 7390737Abstract: A method in which a base layer is deposited in a contact hole region under a protective gas, where base layer contains a nitride as main constituent. After the deposition of the base layer, a covering layer is deposited under gaseous nitrogen. An adhesion promoting layer results which is simple to produce and has good electrical properties.Type: GrantFiled: March 17, 2003Date of Patent: June 24, 2008Assignee: Infineon Technologies AgInventors: Jürgen Förster, Klemens Prügl, Berthold Schuderer
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Publication number: 20080136032Abstract: A method in which a base layer is deposited in a contact hole region under a protective gas, where base layer contains a nitride as main constituent. After the deposition of the base layer, a covering layer is deposited under gaseous nitrogen. An adhesion promoting layer results which is simple to produce and has good electrical properties.Type: ApplicationFiled: February 15, 2008Publication date: June 12, 2008Inventors: Jurgen Forster, Klemens Prugl, Berthold Schuderer
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Publication number: 20080067682Abstract: A bonding pad on a substrate has a first metal structure establishing an electrical connection between a device and a bonding area, and a second metal structure arranged at the bonding area. The first metal structure extends, within the bonding area, at least over part of the bonding area between the substrate and the second metal structure, so as to contact the second metal structure, the second metal structure being harder than the first metal structure.Type: ApplicationFiled: September 12, 2007Publication date: March 20, 2008Inventors: Carsten Ahrens, Sven Albers, Klaus Gnannt, Ulrich Krumbein, Gunther Mackh, Patrick Schelauske, Berthold Schuderer, Georg Seidemann
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Publication number: 20060024946Abstract: A method in which a base layer is deposited in a contact hole region under a protective gas, where base layer contains a nitride as main constituent. After the deposition of the base layer, a covering layer is deposited under gaseous nitrogen. An adhesion promoting layer results which is simple to produce and has good electrical properties.Type: ApplicationFiled: March 17, 2003Publication date: February 2, 2006Inventors: Jurgen Forster, Klemens Prugl, Berthold Schuderer