Patents by Inventor Berthold Schuderer

Berthold Schuderer has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 9312226
    Abstract: A semiconductor device includes a chip, a contact pad arranged over the front side of the chip and an identification mark arranged over the contact pad. The identification mark includes an information about a property of the chip.
    Type: Grant
    Filed: December 14, 2012
    Date of Patent: April 12, 2016
    Assignee: Infineon Technologies AG
    Inventors: Stefan Martens, Berthold Schuderer, Mathias Vaupel, Raimund Peichl
  • Publication number: 20160086842
    Abstract: A method for producing a semiconductor device having a sidewall insulation includes providing a semiconductor body having a first side and a second side lying opposite the first side. At least one first trench is at least partly filled with insulation material proceeding from the first side in the direction toward the second side into the semiconductor body. The at least one first trench is produced between a first semiconductor body region for a first semiconductor device and a second semiconductor body region for a second semiconductor device. An isolating trench extends from the first side of the semiconductor body in the direction toward the second side of the semiconductor body between the first and second semiconductor body regions in such a way that at least part of the insulation material of the first trench adjoins at least a sidewall of the isolating trench. The second side of the semiconductor body is partly removed as far as the isolating trench.
    Type: Application
    Filed: December 1, 2015
    Publication date: March 24, 2016
    Inventors: CARSTEN AHRENS, RUDOLF BERGER, MANFRED FRANK, UWE HOECKELE, BERNHARD KNOTT, ULRICH KRUMBEIN, WOLFGANG LEHNERT, BERTHOLD SCHUDERER, JUERGEN WAGNER, STEFAN WILLKOFER
  • Patent number: 9236290
    Abstract: A method for producing a semiconductor device having a sidewall insulation includes providing a semiconductor body having a first side and a second side lying opposite the first side. At least one first trench is at least partly filled with insulation material proceeding from the first side in the direction toward the second side into the semiconductor body. The at least one first trench is produced between a first semiconductor body region for a first semiconductor device and a second semiconductor body region for a second semiconductor device. An isolating trench extends from the first side of the semiconductor body in the direction toward the second side of the semiconductor body between the first and second semiconductor body regions in such a way that at least part of the insulation material of the first trench adjoins at least a sidewall of the isolating trench. The second side of the semiconductor body is partly removed as far as the isolating trench.
    Type: Grant
    Filed: February 3, 2012
    Date of Patent: January 12, 2016
    Assignee: Infineon Technologies AG
    Inventors: Carsten Ahrens, Rudolf Berger, Manfred Frank, Uwe Hoeckele, Bernhard Knott, Ulrich Krumbein, Wolfgang Lehnert, Berthold Schuderer, Juergen Wagner, Stefan Willkofer
  • Publication number: 20140167272
    Abstract: A semiconductor device includes a chip, a contact pad arranged over the front side of the chip and an identification mark arranged over the contact pad. The identification mark includes an information about a property of the chip.
    Type: Application
    Filed: December 14, 2012
    Publication date: June 19, 2014
    Applicant: INFINEON TECHNOLOGIES AG
    Inventors: Stefan Martens, Berthold Schuderer, Mathias Vaupel, Raimund Peichl
  • Patent number: 8753982
    Abstract: A method for producing a connection region on a side wall of a semiconductor body is disclosed. A first trench is produced on a first surface of a semiconductor body and extends into the semiconductor body. An insulation layer is formed on the side walls and on the bottom of the first trench, and the first trench is only partially filled. The unfilled part of the first trench is filled with an electrically conductive material. A separating trench is produced along the first trench in such a way that a side wall of the separating trench directly adjoins the first trench. The part of the insulation layer which adjoins the separating trench is at least partially removed, with the result that at least some of the electrically conductive material in the first trench is exposed.
    Type: Grant
    Filed: May 10, 2012
    Date of Patent: June 17, 2014
    Assignee: Infineon Technologies AG
    Inventors: Carsten Ahrens, Berthold Schuderer, Stefan Willkofer
  • Patent number: 8637967
    Abstract: A method includes structuring a semiconductor substrate to produce a number semiconductor chips. Each of the semiconductor chips includes a first main face and a number of side faces. An indentation is formed at a transition between the first main face and the side faces.
    Type: Grant
    Filed: November 15, 2010
    Date of Patent: January 28, 2014
    Assignee: Infineon Technologies AG
    Inventors: Markus Menath, Hermann Wendt, Berthold Schuderer
  • Publication number: 20120289023
    Abstract: A method for producing a semiconductor device having a sidewall insulation includes providing a semiconductor body having a first side and a second side lying opposite the first side. At least one first trench is at least partly filled with insulation material proceeding from the first side in the direction toward the second side into the semiconductor body. The at least one first trench is produced between a first semiconductor body region for a first semiconductor device and a second semiconductor body region for a second semiconductor device. An isolating trench extends from the first side of the semiconductor body in the direction toward the second side of the semiconductor body between the first and second semiconductor body regions in such a way that at least part of the insulation material of the first trench adjoins at least a sidewall of the isolating trench. The second side of the semiconductor body is partly removed as far as the isolating trench.
    Type: Application
    Filed: February 3, 2012
    Publication date: November 15, 2012
    Applicant: INFINEON TECHNOLOGIES AG
    Inventors: Carsten Ahrens, Rudolf Berger, Manfred Frank, Uwe Hoeckele, Bernhard Knott, Ulrich Krumbein, Wolfgang Lehnert, Berthold Schuderer, Juergen Wagner, Stefan Willkofer
  • Publication number: 20120289047
    Abstract: A method for producing a connection region on a side wall of a semiconductor body is disclosed. A first trench is produced on a first surface of a semiconductor body and extends into the semiconductor body. An insulation layer is formed on the side walls and on the bottom of the first trench, and the first trench is only partially filled. The unfilled part of the first trench is filled with an electrically conductive material. A separating trench is produced along the first trench in such a way that a side wall of the separating trench directly adjoins the first trench. The part of the insulation layer which adjoins the separating trench is at least partially removed, with the result that at least some of the electrically conductive material in the first trench is exposed.
    Type: Application
    Filed: May 10, 2012
    Publication date: November 15, 2012
    Applicant: INFINEON TECHNOLOGIES AG
    Inventors: Carsten Ahrens, Berthold Schuderer, Stefan Willkofer
  • Publication number: 20120119389
    Abstract: A method includes structuring a semiconductor substrate to produce a number semiconductor chips. Each of the semiconductor chips includes a first main face and a number of side faces. An indentation is formed at a transition between the first main face and the side faces.
    Type: Application
    Filed: November 15, 2010
    Publication date: May 17, 2012
    Inventors: Markus Menath, Hermann Wendt, Berthold Schuderer
  • Patent number: 8163629
    Abstract: In one embodiment, a method for forming the semiconductor device includes forming a first trench from a front side of a substrate. The substrate has a front side and an opposite back side, and the first trench having sidewalls and a bottom surface. A insulator layer is formed over the sidewalls and the bottom surface. A first conductive layer is formed over a top portion of the sidewalls of the first trench. The substrate is separated along the first trench.
    Type: Grant
    Filed: August 5, 2010
    Date of Patent: April 24, 2012
    Assignee: Infineon Technologies AG
    Inventors: Berthold Schuderer, Carsten Ahrens
  • Publication number: 20120034760
    Abstract: In one embodiment, a method for forming the semiconductor device includes forming a first trench from a front side of a substrate. The substrate has a front side and an opposite back side, and the first trench having sidewalls and a bottom surface. A insulator layer is formed over the sidewalls and the bottom surface. A first conductive layer is formed over a top portion of the sidewalls of the first trench. The substrate is separated along the first trench.
    Type: Application
    Filed: August 5, 2010
    Publication date: February 9, 2012
    Inventors: Berthold Schuderer, Carsten Ahrens
  • Patent number: 7825510
    Abstract: A method in which a base layer is deposited in a contact hole region under a protective gas, where base layer contains a nitride as main constituent. After the deposition of the base layer, a covering layer is deposited under gaseous nitrogen. An adhesion promoting layer results which is simple to produce and has good electrical properties.
    Type: Grant
    Filed: February 15, 2008
    Date of Patent: November 2, 2010
    Assignee: Infineon Technologies AG
    Inventors: Jürgen Förster, Klemens Prügl, Berthold Schuderer
  • Patent number: 7816791
    Abstract: A bonding pad on a substrate has a first metal structure establishing an electrical connection between a device and a bonding area, and a second metal structure arranged at the bonding area. The first metal structure extends, within the bonding area, at least over part of the bonding area between the substrate and the second metal structure, so as to contact the second metal structure, the second metal structure being harder than the first metal structure.
    Type: Grant
    Filed: September 12, 2007
    Date of Patent: October 19, 2010
    Assignee: Infineon Technologies AG
    Inventors: Carsten Ahrens, Sven Albers, Klaus Gnannt, Ulrich Krumbein, Gunther Mackh, Patrick Schelauske, Berthold Schuderer, Georg Seidemann
  • Patent number: 7660175
    Abstract: An embodiment of an integrated circuit comprises a plurality of cells. Each cell comprises a first supply node, a second supply node, a series connection with a first transistor, a second transistor and an electrical element. The series connection is coupled between the first and the second supply node. The electrical element includes a first and a second node. A third transistor is coupled between the first node of the electrical element and a first output node of the cell and a fourth transistor is coupled between the second node of the electrical element and the second output node of the cell. A control terminal of the first, the third and the fourth transistor is coupled to a first control node of the cell and a control terminal of the second transistor is coupled to a second control node of the cell.
    Type: Grant
    Filed: February 29, 2008
    Date of Patent: February 9, 2010
    Assignee: Infineon Technologies AG
    Inventors: Dieter Kohlert, Erhard Sixt, Rainer Holmer, Georg Seidemann, Berthold Schuderer, Gunther Mackh, Sabine Penka, Grit Schwalbe-Dietrich, Bernhard Duschinger, Josef Hermann
  • Publication number: 20090219773
    Abstract: An embodiment of an integrated circuit comprises a plurality of cells. Each cell comprises a first supply node, a second supply node, a series connection with a first transistor, a second transistor and an electrical element. The series connection is coupled between the first and the second supply node. The electrical element includes a first and a second node. A third transistor is coupled between the first node of the electrical element and a first output node of the cell and a fourth transistor is coupled between the second node of the electrical element and the second output node of the cell. A control terminal of the first, the third and the fourth transistor is coupled to a first control node of the cell and a control terminal of the second transistor is coupled to a second control node of the cell.
    Type: Application
    Filed: February 29, 2008
    Publication date: September 3, 2009
    Inventors: Dieter Kohlert, Erhard Sixt, Rainer Holmer, Georg Seidemann, Berthold Schuderer, Gunther Mackh, Sabine Penka, Grit Schwalbe-Dietrich, Bernhard Duschinger, Josef Hermann
  • Patent number: 7390737
    Abstract: A method in which a base layer is deposited in a contact hole region under a protective gas, where base layer contains a nitride as main constituent. After the deposition of the base layer, a covering layer is deposited under gaseous nitrogen. An adhesion promoting layer results which is simple to produce and has good electrical properties.
    Type: Grant
    Filed: March 17, 2003
    Date of Patent: June 24, 2008
    Assignee: Infineon Technologies Ag
    Inventors: Jürgen Förster, Klemens Prügl, Berthold Schuderer
  • Publication number: 20080136032
    Abstract: A method in which a base layer is deposited in a contact hole region under a protective gas, where base layer contains a nitride as main constituent. After the deposition of the base layer, a covering layer is deposited under gaseous nitrogen. An adhesion promoting layer results which is simple to produce and has good electrical properties.
    Type: Application
    Filed: February 15, 2008
    Publication date: June 12, 2008
    Inventors: Jurgen Forster, Klemens Prugl, Berthold Schuderer
  • Publication number: 20080067682
    Abstract: A bonding pad on a substrate has a first metal structure establishing an electrical connection between a device and a bonding area, and a second metal structure arranged at the bonding area. The first metal structure extends, within the bonding area, at least over part of the bonding area between the substrate and the second metal structure, so as to contact the second metal structure, the second metal structure being harder than the first metal structure.
    Type: Application
    Filed: September 12, 2007
    Publication date: March 20, 2008
    Inventors: Carsten Ahrens, Sven Albers, Klaus Gnannt, Ulrich Krumbein, Gunther Mackh, Patrick Schelauske, Berthold Schuderer, Georg Seidemann
  • Publication number: 20060024946
    Abstract: A method in which a base layer is deposited in a contact hole region under a protective gas, where base layer contains a nitride as main constituent. After the deposition of the base layer, a covering layer is deposited under gaseous nitrogen. An adhesion promoting layer results which is simple to produce and has good electrical properties.
    Type: Application
    Filed: March 17, 2003
    Publication date: February 2, 2006
    Inventors: Jurgen Forster, Klemens Prugl, Berthold Schuderer