Abstract: A TDM MIMO FMCW radar comprises an array of physical receivers with a first spacing in a first direction and a plurality of physical transmitters arranged with a second spacing in said first direction. A virtual array signal of a range-Doppler bin relating to a scene with a moving object is processed by a phase compensation method, which introduces a phase ambiguity between the subarrays. For each of the subarrays, a frequency spectrum is computed of those elements of the compensated virtual array signal which correspond to consecutive virtual antenna elements generated by physical receivers belonging to the same row. Next, an amplitude-peak frequency is identified jointly for the frequency spectra of the subarrays. Next, a residual phase shift between a pair of the subarrays is determined by comparing, at the amplitude-peak frequency, the respective phases of the frequency spectra.

Abstract: A TDM MIMO FMCW radar comprises an array of physical receivers with a first spacing in a first direction and a plurality of physical transmitters arranged with a second spacing in said first direction. A virtual array signal of a range-Doppler bin relating to a scene with a moving object is processed by a phase compensation method, which introduces a phase ambiguity between the subarrays. A positive or negative spatial phase change rate with respect to the first direction is computed based on elements of the compensated virtual array signal corresponding to one subarray at a time. From this, based on the spacings, a spatial phase change between a pair of the subarrays is predicted. Next, a residual phase shift between said pair of subarrays is determined by comparing an actual phase shift of the compensated virtual array signal and the predicted spatial phase shift.

Abstract: Converters and a corresponding method for converting serial data to parallel format and vice versa, particularly for use in switches for telecommunications applications. The converters comprise a storage element associated with each serial channel and comprising two arrays of storage elements. At any one time, the storage elements are accessed sequentially while those of the other array are accessed in parallel. A data bus, divided into portions by buffers, connects the by buffers, connects the serial channel to all storage cells in an associated storage element. For serial to parallel conversion, the buffers latch data from one bus portion to the next in accordance with a write cycle during which one storage element is written. Writing commences from the bus portion furthest from the incoming serial channel and storage elements on either side of a buffer are written simultaneously. The resulting delay between writing arrays words allows checking of the data such as synchronization.

Abstract: The invention relates to a buffer memory, method and a buffer controller for queue management usable in an ATM switch. An object of the invention is to achieve a high frequency throughput of data cells in the buffer memory. This object is achieved by using a buffer memory which is organized as 256*(424+8) SRAM-cells. The memory is used for holding ten queues, one for each incoming channel and two free-queues containing idle cells.