Abstract: A circuit architecture for computing the outputs of odd and even symmetric spatial filters simultaneously comprises at least two resistive networks interconnected by at least one controlled current source. In one embodiment the nodes of the resistive network are arranged in a two-dimensional array to allow filtering of two-dimensional signals such as images. The resulting filters are orientation selective. The spatial orientation and the scale of the filter can be selected by appropriately tuning the resistive elements forming the resistive networks and the gains of the controlled sources. The controlled sources may be voltage controlled (eg transconductance amplifiers) or current controlled. This circuit architecture may be implemented in VLSI to incorporate both image sensing and orientation selective filtering on the same chip.