Abstract: A signal processor for use in a small, lightweight radar-guided missile to provide a discrete Fast Fourier Transform (FFT) on received radar return signals. The radar return signal are converted into a sequence of binary digits enabling a simple decoder to perform complex addition and subtraction processing, thereby minimizing the space and complexity of the signal processor.

Abstract: A signal processor for use in a small, lightweight radar-guided missile to provide a discrete Fast Fourier Transform (FFT) on received radar return signals. The radar return signals are converted into a sequence of binary digits enabling a simple decoder to perform complex addition and subtraction processing, thereby minimizing the space and complexity of the signal processor.

Abstract: A method is described for improving the operation of a digital pulse compression radar by compensating for amplitude variations in the modulation signal of the transmitted pulse. In the disclosed embodiment, the contemplated compensation is effected by modifying the stored complex conjugate of the frequency spectrum of the transmitted waveform.

Abstract: A method for correcting errors due to imbalances between the two channels of a quadrature demodulator in a radar system is shown. The contemplated method comprises generally the steps of measuring, by performing a Fourier transform on a test signal periodically impressed on the quadrature demodulator, the amplitude and phase imbalances between such channels and then deriving correction coefficients to compensate for such imbalances during operation.

Abstract: An analog-to-digital converter is adapted to operate with input signals having relatively large signal level variations, with the mean level of such signal centered at the midpoint in the operating range of the converter. The converter includes a series of cascade encoding stages, each one providing a digital output signal and a residue output signal, the latter such signal being passed as the input to the succeeding encoding stage. Each one of the cascaded encoding stages includes means for producing an analog residue output signal having a linear relationship to the analog signal applied to each such stage in the middle region of the operating range of each such stage. Such means includes a pair of amplifiers having diode-resistor feedback arrangements.