Abstract: A procedure is provided for identifying an operating mode of a device, such as an EEPROM memory that communicates according to a communication protocol, such as “I2C” (Inter Integrated Circuit). The signal is an “ACK” or “ACKNOWLEDGE” signal. At least one operating mode of a device is identified by a time lag from the time the signal (ACK) is transmitted relative to the time foreseen by the protocol for the signal. This approach can be used to verify that the test mode commands (read or write) have been taken into account correctly.

Abstract: A method is provided for erasing or programming at least one memory cell of a non-volatile memory. According to the method, a state fixation pulse is applied to a floating gate transistor of the memory cell. The state fixation pulse also includes, successively, a portion at a reference voltage, and a state fixation portion at a voltage with sufficient amplitude for the transfer of electrons between the drain and the gate of the floating gate transistor. Additionally, an external adjustment signal is applied to the memory to adjust the state fixation portion to a predetermined duration, and the state fixation portion is adjusted to the predetermined duration in real time as a function of the state of the adjustment signal. Also provided is a non-volatile memory.

Abstract: A method is provided for erasing or programming at least one memory cell of a non-volatile memory. According to the method, a state fixation pulse is applied to a floating gate transistor of the memory cell. The state fixation pulse also includes, successively, a portion at a reference voltage, and a state fixation portion at a voltage with sufficient amplitude for the transfer of electrons between the drain and the gate of the floating gate transistor. Additionally, an external adjustment signal is applied to the memory to adjust the state fixation portion to a predetermined duration, and the state fixation portion is adjusted to the predetermined duration in real time as a function of the state of the adjustment signal. Also provided is a non-volatile memory.

Abstract: A procedure is provided for identifying an operating mode of a device, such as an EEPROM memory that communicates according to a communication protocol, such as “I2C” (Inter Integrated Circuit). The signal is an “ACK” or “ACKNOWLEDGE” signal. At least one operating mode of a device is identified by a time lag from the time the signal (ACK) is transmitted relative to the time foreseen by the protocol for the signal. This approach can be used to verify that the test mode commands (read or write) have been taken into account correctly.

Abstract: A comparator with two thresholds includes a two-threshold latch in which one input and one output respectively form an input and an output of the comparator. The latch has a first node between a first power supply terminal and the output of the latch. The comparator also includes a first negative feedback loop acting on the first node for setting the first threshold of the comparator as a function of a first power supply potential. The first threshold is also a function of a first reference potential that is stable.

Abstract: An electrically programmable and erasable memory includes memory cells connected to word lines and to bit lines arranged in columns. Bit lines selection transistors are driven by bit lines selection signals. Column selection latches each includes a locking element for a column selection signal and a circuit for delivering a gate control signal which depends on the output of the locking element. Each column selection latch delivers, in addition to a gate control signal, a bit lines selection signal. This signal depends on the output of the locking element at least during programming and reading phases of the memory cells.

Abstract: A circuit produces a voltage for the erasure or programming of a memory cell. The circuit includes a capacitor, and a discharge circuit connected to a first terminal of the capacitor. The discharge circuit includes a first transistor, a drain of which is connected to the first terminal of the capacitor. The first transistor activates the discharge circuit when a discharge signal is received by a gate of the first transistor. The discharge circuit includes a slow discharge arm and a fast discharge arm parallel-connected to the source of the first transistor. The discharge circuit produces a low discharge current or a high discharge current for discharging the capacitor as a function of an operating mode selection signal.

Abstract: A method of writing in page mode in an electrically erasable and programmable non-volatile memory includes an initialization phase of writing an information element for the selection of the page in a storage latch associated with a column of the non-volatile memory array, and the writing in a temporary memory of each of the data bits to be written in the page. A write phase includes the selection of rows of the non-volatile memory array according to the contents of the temporary memory. A page mode write circuit includes one latch per column of the non-volatile memory array to contain a page selection information element, and a control logic circuit to give the row selection signals as a function of the contents of the temporary memory in a phase for writing the column of the non-volatile memory array.

Abstract: An electrically programmable and erasable memory includes memory cells connected to word lines and to bit lines arranged in columns. Bit lines selection transistors are driven by bit lines selection signals. Column selection latches each includes a locking element for a column selection signal and a circuit for delivering a gate control signal which depends on the output of the locking element. Each column selection latch delivers, in addition to a gate control signal, a bit lines selection signal. This signal depends on the output of the locking element at least during programming and reading phases of the memory cells.

Abstract: A circuit produces a voltage for the erasure or programming of a memory cell. The circuit includes a capacitor, and a discharge circuit connected to a first terminal of the capacitor. The discharge circuit includes a first transistor, a drain of which is connected to the first terminal of the capacitor. The first transistor activates the discharge circuit when a discharge signal is received by a gate of the first transistor. The discharge circuit includes a slow discharge arm and a fast discharge arm parallel-connected to the source of the first transistor. The discharge circuit produces a low discharge current or a high discharge current for discharging the capacitor as a function of an operating mode selection signal.

Abstract: An integrated circuit electrically is supplied with a voltage and includes an output MOS transistor having a gate driven by an output of a logic circuit and a circuit for biasing the gate of the output MOS transistor. The circuit for biasing the gate is provided for lowering a gate-source bias voltage of the output MOS transistor in a conductive state in relation to the gate-source bias voltage that would otherwise be provided by the output of the logic circuit. The present invention is particularly applicable to output stages for I2C buses.

Abstract: A column register of an integrated circuit memory, notably in EEPROM technology, is utilized in a method of writing a data word of 2p bits in the memory, where p is a non-zero whole number. The method includes the following steps: 1) erasing all the cells of the word; 2) loading 2q data in 2q high-voltage latches (HV1, HV3, HV5, HV7), and loading 2p-2q other data in the 2p-2q low-voltage latches (LV0, LV2, LV4, LV6); and 3) programming 2q cells of the memory (M0, M2, M4, M6) as a function of the data memorized in the 2q high-voltage latches; as well as repeating 2p-q−1 times the following steps: 4) loading, in the 2q high-voltage latches, of 2q other data that were loaded in the 2q low-voltage latches at step 2); and 5) programming 2q other cells of the memory (M1, M3, M5, M7) as a function of the data memorized in the 2q high-voltage latches.

Abstract: An integrated circuit serial access type memory, notably in EEPROM technology, includes a data input (DI) and a data output (DO), a defined memory plane (MM) organized in memory words, as well as a set (LAT) of column registers, one such register being associated with at least one memory word of the memory. The memory includes a writing circuit and/or a reading circuit. The writing circuit operates, during an operation for writing a binary word in a given memory word (M0-M7), for loading the binary data of the binary word received in series at the data input (DI) directly into respective storage and switching latches (HV0-HV7) of the column register (R1) associated with the memory word (M0-M7). The reading circuit operates, during an operation for reading a binary word in a memory word, for reading successively the binary data stored in the memory cells of the memory word and for delivering directly, in serial form, each binary data read to the data output (DO) of the memory.

Abstract: A column register of an integrated circuit memory, notably in EEPROM technology, is utilized in a method of writing a data word of 2P bits in the memory, where p is a non-zero whole number.

Abstract: The invention proposes a method of selecting a determined access line of a serial access type integrated circuit memory, a determined access line being selectable among a determined group of access lines (AL0-AL7) of the same nature, for example a group of bit lines or a group of word lines, a line code on p bits being respectively associated to each access line of the group, which consists in pre-activating all the access lines of the group, then ofdeactivating progressively the other access lines as a function of the bits (Ai) of the line code of the access line to select received in series via the serial data input of the memory such that, in the end, only the access line to be selected remains activated.

Abstract: A column register of an integrated circuit memory, notably in EEPROM technology, is utilized in a method of writing a data word of 2p bits in the memory, where p is a non-zero whole number. The method includes the following steps: 1) erasing all the cells of the word; 2) loading 2q data in 2q high-voltage latches (HV1, HV3, HV5, HV7), and loading 2p−2q other data in the 2p−2q low-voltage latches (LV0, LV2, LV4, LV6); and 3) programming 2q cells of the memory (M0, M2, M4, M6) as a function of the data memorized in the 2q high-voltage latches; as well as repeating 2p−q−1 times the following steps: 4) loading, in the 2q high-voltage latches, of 2q other data that were loaded in the 2q low-voltage latches at step 2); and 5) programming 2q other cells of the memory (M1, M3, M5, M7) as a function of the data memorized in the 2q high-voltage latches.

Abstract: An integrated circuit electrically is supplied with a voltage and includes an output MOS transistor having a gate driven by an output of a logic circuit and a circuit for biasing the gate of the output MOS transistor. The circuit for biasing the gate is provided for lowering a gate-source bias voltage of the output MOS transistor in a conductive state in relation to the gate-source bias voltage that would otherwise be provided by the output of the logic circuit. The present invention is particularly applicable to output stages for I2C buses.