Abstract: A MRAM cell including a first tunnel barrier layer between a soft ferromagnetic layer having a free magnetization and a first hard ferromagnetic layer having a first storage magnetization. A second tunnel barrier layer is between the soft ferromagnetic layer and a second hard ferromagnetic layer and has a second storage magnetization. The first storage magnetization is freely orientable at a first high predetermined temperature threshold and the second storage magnetization being freely orientable at a second predetermined high temperature threshold. The first high predetermined temperature threshold is higher than the second predetermined high temperature threshold. The MRAM cell can be used as a ternary content addressable memory (TCAM) and store up to three distinct state levels. The MRAM cell has a reduced size and can be made at low cost.

Abstract: A MRAM cell including a first tunnel barrier layer between a soft ferromagnetic layer having a free magnetization and a first hard ferromagnetic layer having a first storage magnetization. A second tunnel barrier layer is between the soft ferromagnetic layer and a second hard ferromagnetic layer and has a second storage magnetization. The first storage magnetization is freely orientable at a first high predetermined temperature threshold and the second storage magnetization being freely orientable at a second predetermined high temperature threshold. The first high predetermined temperature threshold is higher than the second predetermined high temperature threshold. The MRAM cell can be used as a ternary content addressable memory (TCAM) and store up to three distinct state levels. The MRAM cell has a reduced size and can be made at low cost.

Abstract: An MRAM cell including a first tunnel barrier layer between a soft ferromagnetic layer having a free magnetization and a first hard ferromagnetic layer having a first storage magnetization; a second tunnel barrier layer between the soft ferromagnetic layer and a second hard ferromagnetic layer having a second storage magnetization; the first storage magnetization being freely orientable at a first high predetermined temperature threshold and the second storage magnetization being freely orientable at a second predetermined high temperature threshold; the first high predetermined temperature threshold being higher than the second predetermined high temperature threshold. The MRAM cell can be used as a ternary content addressable memory (TCAM) and store up to three distinct state levels. The MRAM cell has a reduced size and can be made at low cost.

Abstract: A magnetic logic unit (MLU) cell includes a first and second magnetic tunnel junction, each including a first magnetic layer having a first magnetization, a second magnetic layer having a second magnetization, and a barrier layer; and a field line for passing a field current such as to generate an external magnetic field adapted to adjust the first magnetization. The first and second magnetic layers and the barrier layer are arranged such that the first magnetization is magnetically coupled antiparallel with the second magnetization through the barrier layer. The MLU cell also includes a biasing device arranged for applying a static biasing magnetic field oriented substantially parallel to the external magnetic field such as to orient the first magnetization at about 90° relative to the second magnetization, the first and second magnetizations being oriented symmetrically relative to the direction of the external magnetic field.

Abstract: An apparatus includes an elongated strap with a first platform and a second platform linked by a connector that is substantially narrower than the first platform and the second platform, where the first platform and the second platform are each configured to receive a stress sensitive device.

Abstract: An apparatus has magnetic logic units a logic circuit configured to receive a serial input bit stream at an input node. Individual bits of data from the serial input bit stream are serially written into individual magnetic logic units without buffering the serial input bit stream between the input node and the individual magnetic logic units. Individual bits of data from individual magnetic logic units are serially read to produce a serial output bit stream on an output node without buffering the serial output bit stream between the individual magnetic logic units and the output node.

Abstract: A magnetic logic unit (MLU) cell includes a first and second magnetic tunnel junction, each including a first magnetic layer having a first magnetization, a second magnetic layer having a second magnetization, and a barrier layer; and a field line for passing a field current such as to generate an external magnetic field adapted to adjust the first magnetization. The first and second magnetic layers and the barrier layer are arranged such that the first magnetization is magnetically coupled antiparallel with the second magnetization through the barrier layer. The MLU cell also includes a biasing device arranged for applying a static biasing magnetic field oriented substantially parallel to the external magnetic field such as to orient the first magnetization at about 90° relative to the second magnetization, the first and second magnetizations being oriented symmetrically relative to the direction of the external magnetic field.

Abstract: An MRAM cell including a first tunnel barrier layer between a soft ferromagnetic layer having a free magnetization and a first hard ferromagnetic layer having a first storage magnetization; a second tunnel barrier layer between the soft ferromagnetic layer and a second hard ferromagnetic layer having a second storage magnetization; the first storage magnetization being freely orientable at a first high predetermined temperature threshold and the second storage magnetization being freely orientable at a second predetermined high temperature threshold; the first high predetermined temperature threshold being higher than the second predetermined high temperature threshold. The MRAM cell can be used as a ternary content addressable memory (TCAM) and store up to three distinct state levels. The MRAM cell has a reduced size and can be made at low cost.

Abstract: A magnetic logic unit (MLU) cell includes a first magnetic tunnel junction and a second magnetic tunnel junction, each magnetic tunnel junction including a first magnetic layer having a first magnetization, a second magnetic layer having a second magnetization, and a tunnel barrier layer between the first and second layer. A field line for passing a field current such as to generate an external magnetic field is adapted to switch the first magnetization. The first magnetic layer is arranged such that the magnetic tunnel junction magnetization varies linearly with the generated external magnetic field. An MLU amplifier includes a plurality of the MLU cells. The MLU amplifier has large gains, extended cut off frequencies and improved linearity.

Abstract: The present disclosure concerns a MRAM cell comprising a first tunnel barrier layer comprised between a soft ferromagnetic layer having a free magnetization and a first hard ferromagnetic layer having a first storage magnetization; a second tunnel barrier layer comprised between the soft ferromagnetic layer and a second hard ferromagnetic layer having a second storage magnetization; the first storage magnetization being freely orientable at a first high predetermined temperature threshold and the second storage magnetization being freely orientable at a second predetermined high temperature threshold; the first high predetermined temperature threshold being higher than the second predetermined high temperature threshold. The MRAM cell can be used as a ternary content addressable memory (TCAM) and store up to three distinct state levels. The MRAM cell has a reduced size and can be made at low cost.

Abstract: The present disclosure concerns a multilevel magnetic element comprising a first tunnel barrier layer between a soft ferromagnetic layer having a magnetization that can be freely aligned and a first hard ferromagnetic layer having a magnetization that is fixed at a first high temperature threshold and freely alignable at a first low temperature threshold. The magnetic element further comprises a second tunnel barrier layer and a second hard ferromagnetic layer having a magnetization that is fixed at a second high temperature threshold and freely alignable at a first low temperature threshold; the soft ferromagnetic layer being comprised between the first and second tunnel barrier layers. The magnetic element disclosed herein allows for writing four distinct levels using only a single current line.

Abstract: The present disclosure concerns a multilevel magnetic element comprising a first tunnel barrier layer between a soft ferromagnetic layer having a magnetization that can be freely aligned and a first hard ferromagnetic layer having a magnetization that is fixed at a first high temperature threshold and freely alignable at a first low temperature threshold. The magnetic element further comprises a second tunnel barrier layer and a second hard ferromagnetic layer having a magnetization that is fixed at a second high temperature threshold and freely alignable at a first low temperature threshold; the soft ferromagnetic layer being comprised between the first and second tunnel barrier layers. The magnetic element disclosed herein allows for writing four distinct levels using only a single current line.

Abstract: The present disclosure concerns a multilevel magnetic element comprising a first tunnel barrier layer between a soft ferromagnetic layer having a magnetization that can be freely aligned and a first hard ferromagnetic layer having a magnetization that is fixed at a first high temperature threshold and freely alignable at a first low temperature threshold. The magnetic element further comprises a second tunnel barrier layer and a second hard ferromagnetic layer having a magnetization that is fixed at a second high temperature threshold and freely alignable at a first low temperature threshold; the soft ferromagnetic layer being comprised between the first and second tunnel barrier layers. The magnetic element disclosed herein allows for writing four distinct levels using only a single current line.

Abstract: The present disclosure concerns a MRAM cell comprising a first tunnel barrier layer comprised between a soft ferromagnetic layer having a free magnetization and a first hard ferromagnetic layer having a first storage magnetization; a second tunnel barrier layer comprised between the soft ferromagnetic layer and a second hard ferromagnetic layer having a second storage magnetization; the first storage magnetization being freely orientable at a first high predetermined temperature threshold and the second storage magnetization being freely orientable at a second predetermined high temperature threshold; the first high predetermined temperature threshold being higher than the second predetermined high temperature threshold. The MRAM cell can be used as a ternary content addressable memory (TCAM) and store up to three distinct state levels. The MRAM cell has a reduced size and can be made at low cost.

Abstract: The present disclosure concerns a multilevel magnetic element comprising a first tunnel barrier layer between a soft ferromagnetic layer having a magnetization that can be freely aligned and a first hard ferromagnetic layer having a magnetization that is fixed at a first high temperature threshold and freely alignable at a first low temperature threshold. The magnetic element further comprises a second tunnel barrier layer and a second hard ferromagnetic layer having a magnetization that is fixed at a second high temperature threshold and freely alignable at a first low temperature threshold; the soft ferromagnetic layer being comprised between the first and second tunnel barrier layers. The magnetic element disclosed herein allows for writing four distinct levels using only a single current line.

Abstract: A metal or silicide buried layer in MOS semiconductor devices provides a drain contact on the upper surface of the device with a greatly reduced resistance. The methods of manufacture include depositing the buried layer, rather than diffusing, so that interference with other components is greatly reduced and spacing between components is reduced to reduce the over-all size of the device.

Abstract: A semiconductor structure for high power integrated circuits is fabricated having a substrate, a first and second epitaxial layer, each having a patterned buried layer, and a third epitaxial layer in which power, logic and analogic devices are formed. The power device is formed in an isolated region of the third epitaxial layer over the buried layers, which provide for good electrical contact to the back of the substrate. The analogic and logic devices are formed in the third epitaxial layer outside the isolated region of the power device. The thickness of the first and second epitaxial layers reduces the NPN parasitic transistor effect. The first epitaxial layer may be fabricated with a lower resistivity to further reduce the parasitic NPN transistor effect. The second epitaxial layer can be of a higher resistivity in order to reduce autodoping of the third epitaxial layer.