Abstract: Electrically programmable memories, in particular EPROMs, generally have an internal signature which can be read by the memory-programming device. This internal signature indicates the origin of the part (manufacturer's identification) and the appropriate programming mode for the part (fast programming, "intelligent" programming, etc.). Here, it is proposed that this information be recorded in a UPROM (unerasable programmable read-only) memory, i.e., in practice an EPROM memory masked by a layer of aluminium which prevents its erasure by ultraviolet rays.

Abstract: Memories in integrated circuit form can have several amplifiers per data contact. To increase the possibilities of redundancy with a given number of redundancy columns without, causing too much space near the memory zone to be occupied by complicated multiplexers, the address AP used to select a single amplifier for each contact is used also to select one group of memories among several groups (as many groups as there are amplifiers per contact) in a defective address storage register. Only the defective addresses of this group are applied to a comparator used to detect whether a defective column address is received by the memory. A correlation is thus set up between the place where the defective column is located and the place where the redundancy column, which will be used to replace it, is located. This correlation results from the simultaneous selection by AP of a group of amplifiers and of a group of defective column addresses connected to these amplifiers.

Abstract: To reduce the number of connections in an electrically programmable memory circuit, a device for the testing of the memory cells is proposed. The test consists in the reading of the current that goes through the cells to which access is had in reading mode. The testing device no longer uses specific testing connections between the cells and the corresponding input/output pins but the operational connections of the reading mode, between the reading amplifiers and the input/output buffers, in short-circuiting the input and the output of the reading amplifiers located in a zone close to the memory cells and the input/output buffers located on the peripheral zone, close to the input/output pins. The means to short-circuit the amplifiers and the buffers are respectively located in a zone close to the memory cells, and in the peripheral zone.

Abstract: In order to improve the access time, in reading mode, to the information elements contained in an integrated circuit memory, especially electrically programmable memories such as EPROMs, a circuit for pre-charging the bit line is used and the build-up speed of the potential of the bit line is increased by making a transistor conductive during the pre-charging stage. This transistor is also designed to applying a programming potential Vpp during the stage for programming of the memory.

Abstract: Integrated circuit memories provided with redundancy means enable the lines or columns of defective cells to be repaired. In order to avoid incompatibility between the addressing modifications due to a "grouped test" and those due to placing a redundant column or line into service, means are provided for the addressing, in grouped test mode, not only of several selected columns or lines of the memory but also of a redundant column or line that may have been put into service to replace a defective one of the selected columns or lines.

Abstract: The disclosure relates to one time programmable or OTP memories. When they are encapsulated in plastic packages, these electrically programmable memories can no longer be erased. Hence, they cannot be programmed in order to be tested before being sold to the customer, as they have to be delivered in non-programmable state. To enable the performance of certain tests, notably speed tests, to be made, it is proposed to simulate the programming of certain cells by prohibiting the reading of these cells when they are designated by the decoder. The memory then behaves as if it had both non-programmed cells and programmed cells (the cells for which the reading voltage is inhibited), whereas they actually comprise only non-programmed cells. A very simple logic circuit enables a simulation of a checkerboard pattern of programmed and non-programmed cells.