Patents by Inventor Bertrand Deleris

Bertrand Deleris has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 9674169
    Abstract: A system and method for writing, updating and reading the static and dynamic identification data for an aeronautical appliance, which is secure, of low weight and simple to implement. The system for writing, updating and reading the static and dynamic identification data includes a data collection device for collecting and storing static and dynamic identification data for an aeronautical appliance, the collection device integrated into the aeronautical appliance and coupled to a computing unit of the aeronautical appliance according to a master-slave communication model, the computing unit always being master of the communication with the collection device, and a reading device for remotely reading at least part of the identification data stored on the collection device.
    Type: Grant
    Filed: April 10, 2014
    Date of Patent: June 6, 2017
    Assignee: AIRBUS OPERATIONS (S.A.S.)
    Inventors: Bertrand Leconte, Thierry Planche, Bertrand Deleris
  • Publication number: 20150121458
    Abstract: A system and method for writing, updating and reading the static and dynamic identification data for an aeronautical appliance, which is secure, of low weight and simple to implement. The system for writing, updating and reading the static and dynamic identification data includes a data collection device for collecting and storing static and dynamic identification data for an aeronautical appliance, the collection device integrated into the aeronautical appliance and coupled to a computing unit of the aeronautical appliance according to a master-slave communication model, the computing unit always being master of the communication with the collection device, and a reading device for remotely reading at least part of the identification data stored on the collection device.
    Type: Application
    Filed: April 10, 2014
    Publication date: April 30, 2015
    Inventors: Bertrand LECONTE, Thierry PLANCHE, Bertrand DELERIS
  • Patent number: 8751744
    Abstract: An integrated circuit comprises trace logic for operably coupling to at least one memory element and for providing trace information for a signal processing system. The trace logic comprises trigger detection logic for detecting at least one trace trigger, memory access logic arranged to perform, upon detection of the at least one trace trigger, at least one read operation for at least one memory location of the at least one memory element associated with the at least one detected trigger, memory content message generation logic arranged to generate at least one memory content message comprising information relating to a result of the at least one read operation performed by the memory access logic, and output logic for outputting the at least one memory content message.
    Type: Grant
    Filed: May 29, 2009
    Date of Patent: June 10, 2014
    Assignee: Freescale Semiconductor, Inc.
    Inventors: Bertrand Deleris, Rich Collins
  • Publication number: 20120072666
    Abstract: An integrated circuit comprises trace logic for operably coupling to at least one memory element and for providing trace information for a signal processing system. The trace logic comprises trigger detection logic for detecting at least one trace trigger, memory access logic arranged to perform, upon detection of the at least one trace trigger, at least one read operation for at least one memory location of the at least one memory element associated with the at least one detected trigger, memory content message generation logic arranged to generate at least one memory content message comprising information relating to a result of the at least one read operation performed by the memory access logic, and output logic for outputting the at least one memory content message.
    Type: Application
    Filed: May 29, 2009
    Publication date: March 22, 2012
    Applicant: FreescaleSemiconductor, Inc.
    Inventors: Bertrand Deleris, Rich Collins
  • Patent number: 7984336
    Abstract: A method of storing data from a plurality of processors comprising the steps of (a) transferring data along a first bus (b) connectable between a first processor and a synchronizing means and operable with a first protocol; (c) synchronizing the synchronizing means with a second processor; and (d) transferring the data along a second bus to a memory of the second processor wherein the second bus is connectable between the synchronizing means and the memory of a second processor and operable with a second protocol.
    Type: Grant
    Filed: May 24, 2006
    Date of Patent: July 19, 2011
    Assignee: Freescale Semiconductor, Inc.
    Inventor: Bertrand Deleris
  • Publication number: 20090310499
    Abstract: A data communication network, includes a transmitting node; a receiving node; and a connection between the transmitting node and the receiving node. The receiving node is arranged to process data received from the transmitting mode via the connection. The network further includes a first measuring unit which is connected with a measuring input to the receiving node. The first measuring unit can determine a first parameter value forming a measure for the data processing capacity of the receiving node. A calculator has an input connected to an output of the measuring unit and can derive from the first parameter value a second parameter value forming a measure for the transmission rate of data from the transmitting node to the receiving node. A transmission control unit has a transmission control input connected to a calculator output and a transmission control output connected to the transmitting node.
    Type: Application
    Filed: August 1, 2006
    Publication date: December 17, 2009
    Applicant: Freescale Semiconductor, Inc.
    Inventors: Eric Perraud, Bertrand Deleris
  • Publication number: 20090249127
    Abstract: A method of storing data from a plurality of processors comprising the steps of (a) transferring data along a first bus (b) connectable between a first processor and a synchronising means and operable with a first protocol; (c) synchronising the synchronising means with a second processor; and (d) transferring the data along a second bus to a memory of the second processor wherein the second bus is connectable between the synchronising means and the memory of a second processor and operable with a second protocol.
    Type: Application
    Filed: May 24, 2006
    Publication date: October 1, 2009
    Applicant: FREESCALE SEMICONDUCTOR, INC.
    Inventor: Bertrand Deleris