Abstract: An apparatus comprising a first circuit and a second circuit. The first circuit may be configured to generate (i) a first signal and a second signal in response to a pump down signal and (ii) a third signal and a fourth signal in response to (i) a pump up signal. The second circuit may be configured to generate (a) a first control signal in response to (i) the first signal and (ii) the third signal and (b) a second control signal in response to (i) the second signal and (ii) the fourth signal.

Abstract: A circuit comprising a pump-up circuit and a pump-down circuit. The pump-up circuit may be configured to generate a pump-up signal in response to (i) a data signal and a clock signal. The pump-down circuit may be configured to generate a pump-down signal in response to (i) the data signal, (ii) the clock signal, and (iii) a quadrature of the clock signal.

Abstract: An apparatus comprising a first circuit and a second circuit. The first circuit may be configured to present a first detected data signal in response to (i) one or more first voltages, (ii) one or more second voltages, and (iii) a first reference voltage having a first common mode offset. The second circuit may be configured to present a second detected data signal in response to (i) said one or more first voltages, (ii) said one or more second voltages, and (iii) a second reference voltage having a second common mode offset.

Abstract: An apparatus comprising a first circuit, a second circuit and a third circuit. The first circuit may be configured to generate a first current in response to a reference voltage. The first current may vary as a function of temperature. The second circuit may be configured to generate a second current to counteract for the variations of the first current. The second current may vary as a function of temperature. The third circuit may be configured to generate a third current in response to the first current and the second current.

Abstract: An architecture comprising a detector, a first pump circuit, a second pump circuit and a comparator. The detector may present a first active operating signal in response to one or more reference signals. In one example, the first active operating signal may be generated in response to a feedback signal having a parameter within a predetermined range. The first pump circuit may be configured to provide a replica pump signal in response to a current adjustment signal and either (i) at least one of the one or more reference signals or (ii) the first active operating signal. The second pump circuit may be configured to provide a voltage control signal in response to the current adjustment signal and either (i) the first active operating signal or (ii) a second, independent active operating signal. The comparator may be configured to provide the current adjustment signal in response to the replica pump signal and the voltage control signal.

Abstract: A circuit comprising a pump-up circuit and a pump-down circuit. The pump-up circuit may be configured to generate a pump-up signal in response to (i) a data signal and a clock signal. The pump-down circuit may be configured to generate a pump-down signal in response to (i) the data signal, (ii) the clock signal, and (iii) a quadrature of the clock signal. The pump-down circuit and the pump-up circuit are generally independent circuits.

Abstract: A multi-stage apparatus used as a voltage controlled oscillator. Each stage includes a first complementary differential current switch and a second complementary differential current switch with a second set of complementary differential current switches having a first complementary differential current switch and a second complementary differential current switch, the two sets of complementary differential current switches are connected in a push pull arrangement. In this arrangement, the outputs of the first complementary differential current switch of the first set of complementary differential current switches and the first complementary differential current switch of the second set of complementary differential current switches are connected with the input of the second complementary differential current switch of the first set of complementary differential current switches.

Abstract: A phase detector detects a transition edge on a received data signal and generates a pump-down reference pulse and a pump-up, variable width pulse indicative of phase to synchronize a local clock with the received data signal. The variable width pulse overlaps in time with the reference pulse. The reference pulse is subtracted from the variable width pulse, and the resulting difference signal is supplied in an integrated format to a voltage controlled oscillator (VCO) that controls the frequency of the local clock. When the phase detector is balanced, the variable width pulse and the reference pulse substantially cancel out one another, providing for relatively reduced jitter for the local clock.

Abstract: A phase detector is described. The phase detector receives a data signal from an external circuit. The phase detector generates a first signal when a transition edge of the clock signal occurs after a transition edge of the data signal. The phase detector generates a second signal when the transition edge of the clock signal occurs before the transition edge of the data signal and generates a third signal when the data signal remains in a same signal state for at least two transition edges of a same type of the clock signal.

Abstract: A translator for translating signals from a CML or ECL circuit to signals that are compatible with CMOS or TTL voltage levels is disclosed. The translator has minimum power consumption and provides switching and drive characteristics that are independent of the threshold voltage, power supply voltage, temperature and process variations. The translator includes the following components: a bias reference generator for receiving a first bias voltage and generating a second bias voltage; an input circuit for receiving the input signals; a cascode circuit for receiving the second bias voltage, having a controlled current and outputting the output signals; and a current-mirror circuit. The first bias voltage is at the mid-point of the logic swing of the input signals, and the bias reference generator provides the second bias voltage to generate the controlled current in the switching stage of the translator.

Abstract: A phase detector is described. The phase detector receives a data signal from an external circuit. The phase detector generates a first signal when a transition edge of the dock signal occurs after a transition edge of the data signal. The phase detector generates a second signal when the transition edge of the dock signal occurs before the transition edge of the data signal and generates a third signal when the data signal remains in a same signal state for at least two transition edges of a same type of the dock signal.

Abstract: A phase-lock loop circuit including a voltage-controlled oscillator for generating a clock signal. The voltage-controlled oscillator includes a plurality of multiplexers coupled in series. The signal generated by the last multiplexer in the series is used as a clock signal. Each of the multiplexers in the series has a select input. Either a first signal or a second signal propagates through the series of multiplexers, depending on a select signal applied to the select inputs of the multiplexers. The second signal is the first signal with a predetermined delay. A 3-input multiplexer is connected to the first and last multiplexers in the series to the form a ring oscillator. The first or second signals output by the last multiplexer in the series is sent to an input of the 3-input multiplexer, and a test signal is sent to a third input of the 3-input multiplexer. The 3-input multiplexer also receives the select signal and a test mode signal.

Abstract: An ECL circuit with power control is disclosed. The ECL circuit comprises a pair of emitter-coupled transistors with a current source transistor having its collector coupled to the coupled-emitters of the pair. Coupled in series with the base of the current source transistor is a first MOS transistor with its gate receiving an enable signal to control the first MOS transistor. As such, an activated first MOS transistor switches on the ECL circuit, and a de-activated first MOS transistor switches off the ECL circuit with no current through the current source transistor to provide a true power down of the ECL circuit. An ECL circuit for translating from CMOS to ECL levels is also disclosed. The ECL circuit comprises a pair of emitter-coupled transistors and first MOS transistor coupled in series with a first base of the pair at one end of the source/drain current path of the first MOS transistor.

Abstract: A PLL architecture is disclosed which incorporates a coarse adjustment feedback loop and a fine adjustment feedback loop together providing a combined error signal to a single VCO. The coarse adjustment feedback loop includes two digital counters set to divide the VCO output frequency by two different numbers. The outputs of the counters are coupled to the inputs of respective phase-frequency detectors, and the pump-up output of one of the detectors and the pump-down output of the other detector are used as the coarse adjustment pump-up and pump-down signals, respectively, in the coarse adjustment feedback loop. The coarse adjustment feedback loop thereby establishes a frequency range limitation for the fine adjustment feedback loop.

Abstract: A logic level translator having a fast rising edge at its output for converting ECL logic levels into TTL logic levels includes a switching transistor having its base adapted to receive an input logic level signal representative of an ECL signal, the collector of the switching transistor being connected to an output node. A clamp delay circuit is interconnected between the collector and the base of the switching transistor for inhibiting the switching transistor from receiving feedback current to its base so as to cause a faster turn-off, thereby producing a fast rising edge response at the output node during a high-to-low transition of the input logic level signal.

Abstract: A circuit arrangement for reducing a reference supply voltage level of a reference generator for an ECL circuit during a power-down mode includes a reference generator for producing a reference supply voltage. A first switching network is connected to the input of the reference generator for disabling of the input of the reference generator in response to a control signal so as to reduce the level of the reference supply voltage. A second switching network is connected to the output of the referenced generator for disabling of the output of the reference generator in response to the control signal.

Abstract: A plurality of locally-distributed ECL slave reference generators positioned throughout a large monolithic integrated circuit device for tracking closely a central master reference generator to provide stable slave reference voltages wherein each of the slave reference generators includes a differential comparator which has first and second inputs coupled to a master reference voltage and a slave reference voltage respectively for comparing the master reference voltage and the slave reference voltage and for generating a difference voltage output. A constant current source is coupled to the differential comparator for establishing a constant current flow through the differential comparator. A negative feedback device is responsive to the difference voltage output for supplying a feedback to the second input of the differential comparator as that the slave reference voltage tracks closely the master reference voltage.