Abstract: An interface between a memory that has "n" address bit inputs and a processor which has "p" address bit outputs (where p<n) and "q" programmable data bit outputs (where q.gtoreq.n-p). The interface includes a logic circuit connected to a byte select bit output, to a memory read-write command bit output and to an appropriately programmed one of the "q" programmable bit outputs of the processor. The logic circuit produces a least significant bit address bit input AI0 defined by the equation AI0=R/W & byte-s OR R/W & I/O0. The interface connects the remaining "p" address bit inputs of the memory succeeding to the "p" address bit outputs of the processor, in order, and connects the remaining "n-p-1" most significant address bit inputs of the memory to the same number of appropriately programmed programmable bit outputs of the processor.