Abstract: A method of storing data during verification of a circuit design by a hardware emulation system, includes, in part, receiving, once in every N emulation clock cycles, P sets of register data each set including M register bits associated with the circuit design. The M register bits of each set in P shift registers are stored during M cycles of a capture clock. The stored bits are shifted out during M*P cycles of the capture clock, where (M+1)*P is less than or equal to N.

Abstract: A method of detecting a fault in a circuit design undergoing hardware emulation, includes, in part, comparing, in each cycle K of a clock and at the hardware emulation system, the cycle K register values of a reference circuit with the cycle K register values of the circuit design undergoing emulation. The method further includes detecting, in each cycle K of the clock and at the hardware emulation system, whether a mismatch exists between the cycle K reference circuit design register values and the cycle K register values of the circuit design undergoing emulation. Alternatively the comparison may be made between the respective signatures computed from the register values. The register values of the reference circuit design for all K cycles may be transferred to the emulation system prior to emulation. Alternatively, for each cycle K, the register values may be transferred to the hardware emulation system during that cycle.

Abstract: Disclosed herein is an apparatus and method for emulating hardware. The apparatus includes a data array configured to store input data for an emulation cycle and a carry chain coupled to the data array receives one or more inputs from the data array. The carry chain is configured to generate output data in response to performing an arithmetic operation by a set of configurable logic gates using the one or more inputs in a pre-determined number of clock cycles. One or more processors are coupled to the carry chain and the data array, and are configured to emulate a logic gate function using at least the input data from the data array or the output data from the carry chain.

Abstract: Disclosed herein are systems and methods of an emulation system. A hardware emulator of an emulation system includes one or more processors configured to generate data in an emulation cycle. Each bit of the generated data is associated with a tag. The hardware emulator may include a compaction unit configured to receive the data generated by the one or more processors, and select one or more bits from total bits of the data based on valid tags associated with the bits of the data. The hardware emulator further includes a data array comprising non-transitory machine-readable storage media configured to store the one or more bits of the data received from the compaction unit.

Abstract: Disclosed herein are systems and methods to generate, by a compiling processor, one or more sets of one or more execution instructions responsive to compiling a netlist file. The method further includes storing, by the compiling processor, a set of execution instructions into an instruction memory of an execution processor. The method further includes generating, by a compiling processor, a set of one or more keephot instructions for the execution processor based upon the set of execution instructions stored into the instruction memory of the execution processor. The method further includes storing, by a compiling processor, the set of keephot instructions into the instruction memory of the execution processor.

Abstract: Systems and methods of emulating application-specific integrated circuits using multiple execution phases, where different inputs and outputs are used or produced by components of the emulation system are disclosed. For example, an OMUX may select and transmit different data over a serial bus based on the execution phase of the emulator system. In another example, a processor or cluster may capture outputted data during a first execution phase, execute instructions for a second execution phase, and then return to the capture outputted data for further processing during a next cycle of the first execution phase.

Abstract: Disclosed herein are components of an emulation system capable of efficiently recreating the functionality a CAM/TCAM memory circuit. Rather than using specialized gates or the existing processors, the embodiments described herein configure/instruct the existing memory circuits of the emulation system to imitate a search engine function that queries the existing RAM circuits, portions of which are reconfigured to function as CAM/TCAM memory. The hardware-based search engine and the repurposed memory (e.g., RAM, SRAM, DRAM) allow an emulation system to emulate the functionality of a CAM/TCAM memory. This can be implemented at a low processing cost to the emulation system, as it provides the ability to store more CAM/TCAM data at a very low cost. It can also use the existing system and emulation buses that other components (e.g., processors) of the system use to communicate with the memory, so expansion of the emulation system may not be required.

Abstract: The present patent document relates to a method to compact trace data generated by emulation processors during emulation of a circuit design, and a hardware functional verification system that compacts trace data. Compaction logic within emulation processor clusters accumulated data bits output from the emulation processors and compacts them into trace data bytes in registers based on enable bits identifying valid trace data according to a compaction scheme. Trace data bytes are further accumulated and compacted into larger trace data bytes in higher level processor clusters of the emulation chip according to a compaction hierarchy, with the compacted trace data bytes stored into a trace array of the emulation chip.

Abstract: The present patent document relates to a method to compact trace data generated by emulation processors during emulation of a circuit design, and a hardware functional verification system that compacts trace data. Compaction logic within emulation processor clusters accumulated data bits output from the emulation processors and compacts them into trace data bytes in registers based on enable bits identifying valid trace data according to a compaction scheme. Trace data bytes are further accumulated and compacted into larger trace data bytes in higher level processor clusters of the emulation chip according to a compaction hierarchy, with the compacted trace data bytes stored into a trace array of the emulation chip.

Abstract: The present patent document relates to a method and apparatus for modeling a flip-flop of a user's circuit design when that circuit design is mapped in a hardware functional verification system including a plurality of interconnected emulation chips, or in a single emulation chip. The flip flop can be modeled in the emulation chip as two stages using only a single instruction, and may be configured by programming a register set. A data block, enable block, and LUT block are provided to model the flip flop, and may operate in one of several modes, including combined and uncombined modes. The data block includes a data array to store and provide previous data inputs and previous states of the modeled flip flop. The disclosed embodiments allow a more efficient use of LUTs for modeling flip flops, including options for resets and global enables, operating in several modes.

Abstract: A method and system of dynamically selecting a memory read port are provided. In one form a method may comprises, in part, processing instructions in the emulation processors of a hardware functional verification system, storing output bits generated by the LUT in a plurality of storage elements, selecting between a plurality of previously-stored LUT output bits and the output port of the data memory, selecting one of the plurality of output bits stored in the storage elements, and sending the current data bit provided at the output port of the data memory to a selection circuit when previously-stored LUT output bits are provided. The disclosed systems and methods provide the ability all inputs to a LUT, even while a memory read port is occupied performing other operations during that emulation step, for example sending a value stored in the memory to another emulation processor using the selection circuit.

Abstract: A method and system of providing additional lookup tables in an emulation processor cluster of an emulation chip of a hardware functional verification system is provided. An indirection table may be used within the processor cluster to provide the commonly-used function tables for the lookup tables (LUTs). The indirection table may be indexed according to a smaller portion of the standard LUT function table provided by an instruction than otherwise needed. The unused function table bits in the instruction may then be used for other purposes, including providing functionality to one or more extra LUTs of the processor cluster, whose function tables may be provided from another indirection table provided for that purpose. Additional processing capacity may thereby be provided for the cluster with a small amount of additional overhead within the emulation chip, while still providing the full range of function tables of the LUTs.

Abstract: A processor-based hardware functional verification system with time shift registers is described. The system includes a processor cluster with a plurality of processors that each have a data inputs and select inputs. Furthermore, a plurality of electronic memories each having a plurality of read ports is associated with the processors, respectively. The time shift registers each have an input in communication with the read ports of the electronic memories and an output in communication with the select inputs of the processors. The system further includes an instruction memory that provides a control signal to each of the time shift registers to store data output from read ports of the electronic memories that can be provided to the processor for evaluation during a subsequent emulation step.

Abstract: A system and method for writing simulation acceleration data from a host workstation to a hardware emulation system without considerably sacrificing emulation speed or sacrificing the emulation capacity available for a user's logic design. According to one embodiment, a system comprises a logic software simulator running on a host workstation; a hardware emulation system having a system bus and an emulator chip, the emulator chip includes: an emulation processor that generates emulation data, and a data array connected to the system bus; and a high-speed interface connecting the host workstation to the system bus of the hardware emulator, wherein simulation acceleration data from the host workstation are written to the data array of the emulator chip using the system bus.

Abstract: A system and method for capturing and delivering emulation data from a hardware emulation system to a simulator running on a host workstation without considerably sacrificing emulation speed or sacrificing the emulation capacity available for a user's logic design. According to one embodiment, a system, comprises a logic software simulator running on a host workstation; a hardware emulation system having a system bus and an emulator chip, the emulator chip includes: an emulation processor cluster, and a capture buffer connected to the system bus; and a high-speed interface connecting the host workstation to the system bus of the hardware emulator, wherein the capture buffer captures a select output of the emulation processor cluster.

Abstract: A system and method for capturing and delivering emulation data from a hardware emulation system to a simulator running on a host workstation without considerably sacrificing emulation speed or sacrificing the emulation capacity available for a user's logic design. According to one embodiment, a system, comprises a logic software simulator running on a host workstation; a hardware emulation system having a system bus and an emulator chip, the emulator chip includes: an emulation processor cluster, and a capture buffer connected to the system bus; and a high-speed interface connecting the host workstation to the system bus of the hardware emulator, wherein the capture buffer captures a select output of the emulation processor cluster.

Abstract: A system and method for writing simulation acceleration data from a host workstation to a hardware emulation system without considerably sacrificing emulation speed or sacrificing the emulation capacity available for a user's logic design. According to one embodiment, a system comprises a logic software simulator running on a host workstation; a hardware emulation system having a system bus arid an emulator chip, the emulator chip includes: an emulation processor that generates emulation data, and a data array connected to the system bus; and a high-speed interface connecting the host workstation to the system bus of the hardware emulator, wherein simulation acceleration data from the host workstation are written to the data array of the emulator chip using the system bus.

Abstract: A processor-based emulation system for emulating an integrated circuit design, the processor-based emulation system including emulation circuitry and capture circuitry. The capture circuitry is operable to capture processing results from the emulation circuitry. The captured processing results can be used to identify functional errors in the integrated circuit design. Because the processor-based emulation system includes capture circuitry, emulation circuitry is not used for capturing the processing results.

Abstract: The present system and methods are directed to the interconnection of clusters of emulation processors comprising emulation processors in a software-driven hardware design verification system. The processors each output one NBO output signal. The clusters are interconnected by partitioning a common NBO bus into a number of smaller NBO busses, each carrying unique NBO signals but together carrying every NBO. Each of the smaller NBO busses are passed into a series of multiplexers, each dedicated to a particular processor. The multiplexers select a signal for output back to the emulation clusters. The multiplexers that handle these smaller NBO busses are narrower than was previously required, thus reducing the amount of power, interconnect, and area required by the multiplexer array and dedicated interconnect.

Abstract: A hardware emulation system having a heterogeneous cluster of processors is described. The apparatus for emulating a hardware design comprises a plurality of processors, where each processor performs a different function during an emulation cycle. The method performed by the apparatus comprises using a data fetch processor to retrieve data from a data array, evaluating the retrieved data using the data fetch processor to produce an output bit, supplying the output bit to an intracluster crossbar and using a data store processor to store the output bit in the data array.