Abstract: A method and apparatus for improving the efficiency of a processor-based emulation engine. The emulation engine is composed of a plurality of processors, each processor capable of emulating a logic gate. Processors are arranged into groups of processors called clusters. Each processor receives inputs, processes the inputs, and stores the outputs in an output array. The output array allows processors within a cluster to fetch an output from a processor that was written to the output array during a previous cycle. The output array can also store and transfer data between clusters of processors. Consequently, the number of cycles that a processor or a cluster has to wait to fetch data is greatly reduced and the efficiency of the emulation engine is increased.

Abstract: A hardware emulation system having a heterogeneous cluster of processors is described. The apparatus for emulating a hardware design comprises a plurality of processors, where each processor performs a different function during an emulation cycle. The method performed by the apparatus comprises using a data fetch processor to retrieve data from a data array, evaluating the retrieved data using the data fetch processor to produce an output bit, supplying the output bit to an intracluster crossbar and using a data store processor to store the output bit in the data array.

Abstract: A hardware emulator having an emulation unit with a shadow processor is described. The shadow processor is capable of performing an extra look up table (LUT) operation in addition to the LUT operation performed by a processor within the emulation unit. The emulation unit comprises a memory for supplying a first amount of data to a shadow processor register, wherein the shadow processor register stores the first amount of data for later retrieval. The data stored in the shadow processor register function as operands for a truth table stored in the memory and are used to select a function bit out from the memory. The selected function bit out represents a Boolean evaluation of the operands.

Abstract: A hardware emulator having a first primitive for evaluating functions having a first input width and a second primitive, coupled to the first primitive, for evaluating a function having a second input width, where the first input width is unequal to the second input width. The use of either the first primitive or the second primitive is selected depending upon the function to be evaluated.

Abstract: A hardware emulator having a variable input emulation group is described. Each emulation group comprises two or more processors, where one of the processors (a first processor) is coupled to a data input selector and another one of the processors (a second processor) processes a first amount of data received from a data array. The data input selector receives the first amount of data and a second amount of data from the data array, and selects a third amount of data from among the first and second amounts of data. The third amount of data is provided to the first processor for evaluation.

Abstract: A method and apparatus for a memory efficient hardware emulator. The emulator comprises a plurality of processor dusters having data within the duster is stored in at least one data array, where the at least one data array comprises a plurality of sub-arrays. The sub-arrays that are not of uniform size (e.g., the size of each sub-array is determined by the probability that a particular sub-array will be accessed by the processor during a future emulation step). For example, at least one first sub-array is equal in depth to instruction memory within a processor (i.e., equal to the number of instructions in an emulation cycle), and the remaining sub-arrays are a fractional depth of the first sub-array.

Abstract: A method and apparatus for coupling data between discrete processor-based emulation chips is described. The apparatus is a processor-based hardware emulation integrated circuits (chips) element comprising a plurality of discrete hardware emulation chips, each emulation chip coupled to another emulation chip by a crossbar for coupling data between the plurality of chips. The method comprises providing data to a crossbar from a first discrete emulation chip, selecting the data from the crossbar using a discrete second emulation chip, and storing the data in a data array in the second discrete emulation chip.

Abstract: A method and apparatus for sharing data between processors within first and second discrete clusters of processors. The method comprises supplying a first amount of data from a first data array in a first discrete cluster of processors to selector logic. A second amount of data from a second data array in a second discrete cluster of processors is also supplied to the selector logic. The first or second amount of data is then selected using the selector logic, and supplied to a shared input port on a processor in the first discrete cluster of processors. The apparatus comprises selector logic for selecting between input data supplied by a first data array and a second data array. The data arrays are located within different discrete clusters of processors. The selected data is then supplied to a shared input port on a processor.