Patents by Inventor Beth Ann Peterson

Beth Ann Peterson has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 11294812
    Abstract: Provided are a computer program product, system, and method for prefetching cache resources for a write request from a host to tracks in storage cached in a cache. Cache resources held for a plurality of tracks in a write set are released before expected writes are received for the tracks in the write set. Cache resources for tracks in the write set are obtained, following the release of the cache resources, to use for expected write requests to the tracks in the write set.
    Type: Grant
    Filed: August 4, 2020
    Date of Patent: April 5, 2022
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Beth Ann Peterson, Chung Man Fung, Matthew J. Kalos, Matthew Richard Craig
  • Publication number: 20220043750
    Abstract: Provided are a computer program product, system, and method for prefetching cache resources for a write request from a host to tracks in storage cached in a cache. Cache resources held for a plurality of tracks in a write set are released before expected writes are received for the tracks in the write set. Cache resources for tracks in the write set are obtained, following the release of the cache resources, to use for expected write requests to the tracks in the write set.
    Type: Application
    Filed: August 4, 2020
    Publication date: February 10, 2022
    Inventors: Beth Ann PETERSON, Chung Man FUNG, Matthew J. KALOS, Matthew Richard CRAIG
  • Publication number: 20220043751
    Abstract: Provided are a computer program product, system, and method for providing track access reasons for track accesses resulting in the release of prefetched cache resources for the track. A first request for a track is received from a process for which prefetched cache resources to a cache are held for a second request for the track that is expected. A track access reason is provided for the first request specifying a reason for the first request. The prefetched cache resources are released before the second request to the track is received. Indication is made in an unexpected released track list of the track and the track access reason for the first request.
    Type: Application
    Filed: August 4, 2020
    Publication date: February 10, 2022
    Inventors: Beth Ann PETERSON, Chung Man FUNG, Matthew J. KALOS, Warren Keith STANLEY, Matthew J. WARD
  • Patent number: 11243885
    Abstract: Provided are a computer program product, system, and method for providing track access reasons for track accesses resulting in the release of prefetched cache resources for the track. A first request for a track is received from a process for which prefetched cache resources to a cache are held for a second request for the track that is expected. A track access reason is provided for the first request specifying a reason for the first request. The prefetched cache resources are released before the second request to the track is received. Indication is made in an unexpected released track list of the track and the track access reason for the first request.
    Type: Grant
    Filed: August 4, 2020
    Date of Patent: February 8, 2022
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Beth Ann Peterson, Chung Man Fung, Matthew J. Kalos, Warren Keith Stanley, Matthew J. Ward
  • Publication number: 20220027267
    Abstract: A computer-implemented method, according to one approach, includes: determining whether to satisfy an I/O request using a first tier of memory in a secondary cache by inspecting a bypass indication in response to determining that the input/output (I/O) request includes a bypass indication. The secondary cache is coupled to a primary cache and a data storage device. The secondary cache also includes the first tier of memory and a second tier of memory. Moreover, in response to determining to satisfy the I/O request using the first tier of memory in the secondary cache, the I/O request is satisfied using the first tier of memory in the secondary cache. The updated data is also destaged from the secondary cache to the data storage device in response to determining that data associated with the I/O request has been updated as the result of satisfying the I/O request using the secondary cache.
    Type: Application
    Filed: October 5, 2021
    Publication date: January 27, 2022
    Inventors: Lokesh Mohan Gupta, Edward Hsiu-Wei Lin, Beth Ann Peterson, Matthew G. Borlick
  • Patent number: 11210237
    Abstract: Indications of a minimum retention time and a maximum retention time in a cache comprising a first type of memory and a second type of memory are received from a host application for a first plurality of tracks, wherein the minimum retention time or the maximum retention time are not indicated for a second plurality of tracks. In response to accessing a track of the first plurality of tracks, the minimum retention time is set for the track for the first type of memory, and the maximum retention time is set for the track for the second type of memory.
    Type: Grant
    Filed: February 13, 2020
    Date of Patent: December 28, 2021
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Lokesh Mohan Gupta, Kyler A. Anderson, Beth Ann Peterson, Matthew G. Borlick
  • Patent number: 11182291
    Abstract: A computer-implemented method, according to one approach, includes: receiving an I/O request. In response to determining that the I/O request does not include a bypass indication, the I/O request is satisfied using a primary cache which is coupled to a data storage device and a secondary cache having SCM. In response to determining that the data associated with the I/O request has been updated as a result of satisfying the I/O request: the updated data is destaged from the primary cache to the data storage device, the updated data is copied to the secondary cache, and the updated data is demoted from the primary cache. Yet, in response to determining that the data associated with the I/O request has not been updated: the data associated with the I/O request is copied to the secondary cache, and the data associated with the I/O request is demoted from the primary cache.
    Type: Grant
    Filed: February 3, 2020
    Date of Patent: November 23, 2021
    Assignee: International Business Machines Corporation
    Inventors: Lokesh Mohan Gupta, Edward Hsiu-Wei Lin, Beth Ann Peterson, Matthew G. Borlick
  • Patent number: 11176057
    Abstract: An indication is received from a host application of a first minimum retention time in a cache comprising a first type of memory and a second type of memory for a first plurality of tracks, wherein the first minimum retention time is not indicated for a second plurality of tracks. Based on the first minimum retention time, a second minimum retention time is set for the first plurality of tracks for the first type of memory and a third minimum retention time is set for the first plurality of tracks for the second type of memory. A track of the first plurality of tracks is demoted from the first type of memory, in response to determining that the track is a least recently used (LRU) track in a LRU list of tracks in the first type of memory and the track has been in the first type of memory for a time that exceeds the second minimum retention time.
    Type: Grant
    Filed: February 13, 2020
    Date of Patent: November 16, 2021
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Lokesh Mohan Gupta, Matthew G. Borlick, Beth Ann Peterson, Kyler A. Anderson
  • Patent number: 11175959
    Abstract: A machine learning module receives inputs comprising attributes of a storage controller, wherein the attributes affect allocation of a plurality of resources to a plurality of interfaces. In response to a predetermined number of I/O operations occurring in the storage controller, a generation is made via forward propagation through a plurality of layers of the machine learning module, of an output value corresponding to a number of resources to allocate to an interface. A margin of error is calculated based on comparing the generated output value to an expected output value that is generated from an indication of a predetermined function based at least on a number of I/O operations that are waiting for a resource and a number of available resources. An adjustment is made of weights of links that interconnect nodes of the plurality of layers via back propagation, to reduce the margin of error.
    Type: Grant
    Filed: May 1, 2019
    Date of Patent: November 16, 2021
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Lokesh M. Gupta, Matthew R. Craig, Beth Ann Peterson, Kevin John Ash
  • Patent number: 11175958
    Abstract: A plurality of interfaces that share a plurality of resources in a storage controller are maintained. In response to an occurrence of a predetermined number of operations associated with an interface of the plurality of interfaces, an input is provided on a plurality of attributes of the storage controller to a machine learning module. In response to receiving the input, the machine learning module generates an output value corresponding to a number of resources of the plurality of resources to allocate to the interface in the storage controller.
    Type: Grant
    Filed: May 1, 2019
    Date of Patent: November 16, 2021
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Lokesh M. Gupta, Matthew R. Craig, Beth Ann Peterson, Kevin John Ash
  • Patent number: 11169933
    Abstract: An indication of a maximum retention time in a cache comprising a first type of memory and a second type of memory for a first plurality of tracks is received from a host application, wherein no maximum retention time is indicated for a second plurality of tracks. In response to demoting a track of the first plurality of tracks from the first type of memory to the second type of memory, an adjustment of a first amount of time that the track is allowed to be retained in the second type of memory is based on a second amount of time the track has already been present in the first type of memory prior to being demoted from the first type of memory to the second type of memory.
    Type: Grant
    Filed: February 13, 2020
    Date of Patent: November 9, 2021
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Lokesh Mohan Gupta, Matthew G. Borlick, Kyler A. Anderson, Beth Ann Peterson
  • Publication number: 20210312829
    Abstract: A method is disclosed to ensure that components in a complex system are correctly connected together. In one embodiment, such a method provides a library of previous configurations of a system. The system includes multiple components connected together with cables. The method generates, from the library, instructions for assembling the system by connecting components of the system together with cables. The method receives feedback generated in the course of using the instructions to assemble the system and uses the feedback to refine the instructions. In certain embodiments, a configuration associated with the assembled system is then added to the library. This process may be repeated to further refine the instructions and increase a number of configurations in the library. A corresponding apparatus and computer program product are also disclosed.
    Type: Application
    Filed: April 1, 2020
    Publication date: October 7, 2021
    Applicant: International Business Machines Corporation
    Inventors: Beth Ann Peterson, Paulina Acevedo, Veronica A. Reeves-Voeltner, Samantha A. Utter
  • Publication number: 20210279174
    Abstract: A computer-implemented method, according to one approach, includes: receiving a stream of incoming I/O requests, all of which are satisfied using one or more buffers in a primary cache. However, in response to determining that the available capacity of the one or more buffers in the primary cache is outside a predetermined range: one or more buffers in the secondary cache are allocated. These one or more buffers in the secondary cache are used to satisfy at least some of the incoming I/O requests, while the one or more buffers in the primary cache are used to satisfy a remainder of the incoming I/O requests. Moreover, in response to determining that the available capacity of the one or more buffers in the primary cache is not outside the predetermined range: the one or more buffers in the primary cache are again used to satisfy all of the incoming I/O requests.
    Type: Application
    Filed: March 9, 2020
    Publication date: September 9, 2021
    Inventors: Beth Ann Peterson, Kevin J. Ash, Lokesh Mohan Gupta, Warren Keith Stanley, Roger G. Hathorn
  • Publication number: 20210263863
    Abstract: A computer-implemented method, according to one approach, includes: initiating an I/O request using a primary cache, where the I/O request includes supplemental information pertaining to an anticipated workload of the I/O request. Performance characteristics experienced by the primary cache while satisfying the I/O request are also evaluated. The supplemental information and the performance characteristics are further used to determine whether to satisfy a remainder of the I/O request using the secondary cache. In response to determining to satisfy a remainder of the I/O request using the secondary cache, the I/O request is demoted from the primary cache to the secondary cache, and a remainder of the I/O request is satisfied using the secondary cache. However, in response to determining to not satisfy a remainder of the I/O request using the secondary cache, a remainder of the I/O request is satisfied using the primary cache.
    Type: Application
    Filed: April 23, 2021
    Publication date: August 26, 2021
    Inventors: Beth Ann Peterson, Chung Man Fung, Lokesh Mohan Gupta, Kyler A. Anderson
  • Publication number: 20210255965
    Abstract: An indication of a maximum retention time in a cache comprising a first type of memory and a second type of memory for a first plurality of tracks is received from a host application, wherein no maximum retention time is indicated for a second plurality of tracks. In response to demoting a track of the first plurality of tracks from the first type of memory to the second type of memory, an adjustment of a first amount of time that the track is allowed to be retained in the second type of memory is based on a second amount of time the track has already been present in the first type of memory prior to being demoted from the first type of memory to the second type of memory.
    Type: Application
    Filed: February 13, 2020
    Publication date: August 19, 2021
    Inventors: Lokesh Mohan Gupta, Matthew G. Borlick, Kyler A. Anderson, Beth Ann Peterson
  • Publication number: 20210255964
    Abstract: An indication is received from a host application of a first minimum retention time in a cache comprising a first type of memory and a second type of memory for a first plurality of tracks, wherein the first minimum retention time is not indicated for a second plurality of tracks. Based on the first minimum retention time, a second minimum retention time is set for the first plurality of tracks for the first type of memory and a third minimum retention time is set for the first plurality of tracks for the second type of memory. A track of the first plurality of tracks is demoted from the first type of memory, in response to determining that the track is a least recently used (LRU) track in a LRU list of tracks in the first type of memory and the track has been in the first type of memory for a time that exceeds the second minimum retention time.
    Type: Application
    Filed: February 13, 2020
    Publication date: August 19, 2021
    Inventors: Lokesh Mohan Gupta, Matthew G. Borlick, Beth Ann Peterson, Kyler A. Anderson
  • Publication number: 20210255967
    Abstract: Indications of a minimum retention time and a maximum retention time in a cache comprising a first type of memory and a second type of memory are received from a host application for a first plurality of tracks, wherein the minimum retention time or the maximum retention time are not indicated for a second plurality of tracks. In response to accessing a track of the first plurality of tracks, the minimum retention time is set for the track for the first type of memory, and the maximum retention time is set for the track for the second type of memory.
    Type: Application
    Filed: February 13, 2020
    Publication date: August 19, 2021
    Inventors: Lokesh Mohan Gupta, Kyler A. Anderson, Beth Ann Peterson, Matthew G. Borlick
  • Publication number: 20210240618
    Abstract: A computer-implemented method, according to one approach, includes: receiving an I/O request. In response to determining that the I/O request does not include a bypass indication, the I/O request is satisfied using a primary cache which is coupled to a data storage device and a secondary cache having SCM. In response to determining that the data associated with the I/O request has been updated as a result of satisfying the I/O request: the updated data is destaged from the primary cache to the data storage device, the updated data is copied to the secondary cache, and the updated data is demoted from the primary cache. Yet, in response to determining that the data associated with the I/O request has not been updated: the data associated with the I/O request is copied to the secondary cache, and the data associated with the I/O request is demoted from the primary cache.
    Type: Application
    Filed: February 3, 2020
    Publication date: August 5, 2021
    Inventors: Lokesh Mohan Gupta, Edward Hsiu-Wei Lin, Beth Ann Peterson, Matthew G. Borlick
  • Patent number: 11075754
    Abstract: Various embodiments for configuring a medical database by a processor in communication with at least one storage device in a computing environment are provided. Medical data are assigned to a patient. A plurality of data types is organized for the medical data. Portions of each of the plurality of data types are designated as public and private data. A plurality of access levels is organized for the medical data. Each of the plurality of data types includes the plurality of access levels. A first access level of the plurality of access levels corresponds to the patient. The medical data is classified according to the plurality of data types, for each of the plurality of data types, according to the plurality of access levels, and according to one of the public and the private data. The medical data is encrypted in a hierarchical structure corresponding to each of the plurality of access levels.
    Type: Grant
    Filed: January 15, 2009
    Date of Patent: July 27, 2021
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Theresa M. Brown, Nedlaya Yazzie Francisco, Suguang Li, Beth Ann Peterson
  • Patent number: 11061828
    Abstract: A computer-implemented method, according to one approach, includes: receiving an I/O request which includes supplemental information pertaining to an anticipated workload of the I/O request. The supplemental information is used to determine whether to satisfy the I/O request using a primary cache. In response to determining to satisfy the I/O request using the primary cache, the I/O request is initiated using the primary cache, and performance characteristics experienced by the primary cache while satisfying the I/O request are evaluated. The supplemental information and the performance characteristics are further used to determine whether to satisfy a remainder of the I/O request using the secondary cache. In response to determining to satisfy a remainder of the I/O request using the secondary cache, the I/O request is demoted from the primary cache to the secondary cache, and a remainder of the I/O request is satisfied using the secondary cache.
    Type: Grant
    Filed: February 25, 2020
    Date of Patent: July 13, 2021
    Assignee: International Business Machines Corporation
    Inventors: Beth Ann Peterson, Chung Man Fung, Lokesh Mohan Gupta, Kyler A. Anderson