Patents by Inventor Beth Ann Rainey
Beth Ann Rainey has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
-
Patent number: 8890246Abstract: Integrated circuits having doped bands in a substrate and beneath high-voltage semiconductor-on-insulator (SOI) devices are provided. In one embodiment, the invention provides an integrated circuit comprising: a semiconductor-on-insulator (SOI) wafer including: a substrate; a buried oxide (BOX) layer atop the substrate; and a semiconductor layer atop the BOX layer; a plurality of high voltage (HV) devices connected in series within the semiconductor layer; a doped band within the substrate and below a first of the plurality of HV devices; and a contact extending from the semiconductor layer and through the BOX layer to the doped band.Type: GrantFiled: August 28, 2012Date of Patent: November 18, 2014Assignee: International Business Machines CorporationInventors: Alan B. Botula, Beth Ann Rainey, Yun Shi
-
Publication number: 20120319229Abstract: Integrated circuits having doped bands in a substrate and beneath high-voltage semiconductor-on-insulator (SOI) devices are provided. In one embodiment, the invention provides an integrated circuit comprising: a semiconductor-on-insulator (SOI) wafer including: a substrate; a buried oxide (BOX) layer atop the substrate; and a semiconductor layer atop the BOX layer; a plurality of high voltage (HV) devices connected in series within the semiconductor layer; a doped band within the substrate and below a first of the plurality of HV devices; and a contact extending from the semiconductor layer and through the BOX layer to the doped band.Type: ApplicationFiled: August 28, 2012Publication date: December 20, 2012Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Alan B. Botula, Beth Ann Rainey, Yun Shi
-
Patent number: 8299561Abstract: Integrated circuits having doped bands in a substrate and beneath high-voltage semiconductor-on-insulator (SOI) devices are provided. In one embodiment, the invention provides an integrated circuit comprising: a semiconductor-on-insulator (SOI) wafer including: a substrate; a buried oxide (BOX) layer atop the substrate; and a semiconductor layer atop the BOX layer; a plurality of high voltage (HV) devices connected in series within the semiconductor layer; a doped band within the substrate and below a first of the plurality of HV devices; and a contact extending from the semiconductor layer and through the BOX layer to the doped band.Type: GrantFiled: April 21, 2010Date of Patent: October 30, 2012Assignee: International Business Machines CorporationInventors: Alan B. Botula, Beth Ann Rainey, Yun Shi
-
Publication number: 20110260281Abstract: Integrated circuits having doped bands in a substrate and beneath high-voltage semiconductor-on-insulator (SOI) devices are provided. In one embodiment, the invention provides an integrated circuit comprising: a semiconductor-on-insulator (SOI) wafer including: a substrate; a buried oxide (BOX) layer atop the substrate; and a semiconductor layer atop the BOX layer; a plurality of high voltage (HV) devices connected in series within the semiconductor layer; a doped band within the substrate and below a first of the plurality of HV devices; and a contact extending from the semiconductor layer and through the BOX layer to the doped band.Type: ApplicationFiled: April 21, 2010Publication date: October 27, 2011Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Alan B. Botula, Beth Ann Rainey, Yun Shi
-
Patent number: 7696034Abstract: Methods for fabricating a heterojunction bipolar transistor having a raised extrinsic base is provided in which the base resistance is reduced by forming a silicide atop the raised extrinsic base that extends to the emitter region in a self-aligned manner. The silicide formation is incorporated into a BiCMOS process flow after the raised extrinsic base has been formed. The present invention also provides a heterojunction bipolar transistor having a raised extrinsic base and a silicide located atop the raised extrinsic base. The silicide atop the raised extrinsic base extends to the emitter in a self-aligned manner. The emitter is separated from the silicide by a spacer.Type: GrantFiled: May 28, 2008Date of Patent: April 13, 2010Assignee: International Business Machines CorporationInventors: Peter J. Geiss, Marwan H. Khater, Qizhi Liu, Randy W. Mann, Robert J. Purtell, Beth Ann Rainey, Jae-Sung Rieh, Andreas D. Stricker
-
Publication number: 20080176363Abstract: A field effect transistor (FET) and method of forming the FET comprises a substrate; a silicon germanium (SiGe) layer over the substrate; a semiconductor layer over and adjacent to the SiGe layer; an insulating layer adjacent to the substrate, the SiGe layer, and the semiconductor layer; a pair of first gate structures adjacent to the insulating layer; and a second gate structure over the insulating layer. Preferably, the insulating layer is adjacent to a side surface of the SiGe layer and an upper surface of the semiconductor layer, a lower surface of the semiconductor layer, and a side surface of the semiconductor layer. Preferably, the SiGe layer comprises carbon. Preferably, the pair of first gate structures are substantially transverse to the second gate structure. Additionally, the pair of first gate structures are preferably encapsulated by the insulating layer.Type: ApplicationFiled: July 31, 2007Publication date: July 24, 2008Inventors: Brent A. Anderson, Matthew J. Breitwisch, Edward J. Nowak, Beth Ann Rainey
-
Patent number: 7119416Abstract: The invention includes methods of fabricating a bipolar transistor that adds a silicon germanium (SiGe) layer or a third insulator layer of, e.g., high pressure oxide (HIPOX), atop an emitter cap adjacent the intrinsic base prior to forming a link-up layer. This addition allows for removal of the link-up layer using wet etch chemistries to remove the excess SiGe or third insulator layer formed atop the emitter cap without using oxidation. In this case, an oxide section (formed by deposition of an oxide or segregation of the above-mentioned HIPOX layer) and nitride spacer can be used to form the emitter-base isolation. The invention results in lower thermal cycle, lower stress levels, and more control over the emitter cap layer thickness, which are drawbacks of the first embodiment. The invention also includes the resulting bipolar transistor structure.Type: GrantFiled: June 29, 2005Date of Patent: October 10, 2006Assignee: International Business Machines CorporationInventors: Thomas N. Adam, Kevin K. Chan, Alvin J. Joseph, Marwan H. Khater, Qizhi Liu, Beth Ann Rainey, Kathryn T. Schonenberg
-
Patent number: 7037798Abstract: The invention includes methods of fabricating a bipolar transistor that adds a silicon germanium (SiGe) layer or a third insulator layer of, e.g., high pressure oxide (HIPOX), atop an emitter cap adjacent the intrinsic base prior to forming a link-up layer. This addition allows for removal of the link-up layer using wet etch chemistries to remove the excess SiGe or third insulator layer formed atop the emitter cap without using oxidation. In this case, an oxide section (formed by deposition of an oxide or segregation of the above-mentioned HIPOX layer) and nitride spacer can be used to form the emitter-base isolation. The invention results in lower thermal cycle, lower stress levels, and more control over the emitter cap layer thickness, which are drawbacks of the first embodiment. The invention also includes the resulting bipolar transistor structure.Type: GrantFiled: November 12, 2004Date of Patent: May 2, 2006Assignee: International Business Machines CorporationInventors: Thomas N. Adam, Kevin K. Chan, Alvin J. Joseph, Marwan H. Khater, Qizhi Liu, Beth Ann Rainey, Kathryn T. Schonenberg
-
Patent number: 6888187Abstract: A memory cell that has first and second fully depleted transfer devices each having a body region and first and second diffused electrodes. The cell has a differential storage capacitor having at least one node abutting and in electrical contact with one of the first and second diffused electrodes of each of the transfer devices. The storage capacitor has a primary capacitance and a plurality of inherent capacitances, wherein the primary capacitance has a capaictive value that is at least approximately five times greater than that of the plurality of inherent capacitances.Type: GrantFiled: August 26, 2002Date of Patent: May 3, 2005Assignee: International Business Machines CorporationInventors: Jeffrey S. Brown, David M. Fried, Edward J. Nowak, Beth Ann Rainey
-
Patent number: 6864136Abstract: A memory cell that has first and second fully depleted transfer devices each having a body region and first and second diffused electrodes. The cell has a differential storage capacitor having at least one node abutting and in electrical contact with one of the first and second diffused electrodes of each of the transfer devices. The storage capacitor has a primary capacitance and a plurality of inherent capacitances, wherein the primary capacitance has a capaictive value that is at least approximately five times greater than that of the plurality of inherent capacitances.Type: GrantFiled: December 11, 2003Date of Patent: March 8, 2005Assignee: International Business Machines CorporationInventors: Jeffrey S. Brown, David M. Fried, Edward J. Nowak, Beth Ann Rainey
-
Publication number: 20040126969Abstract: A memory cell that has first and second fully depleted transfer devices each having a body region and first and second diffused electrodes. The cell has a differential storage capacitor having at least one node abutting and in electrical contact with one of the first and second diffused electrodes of each of the transfer devices. The storage capacitor has a primary capacitance and a plurality of inherent capacitances, wherein the primary capacitance has a capaictive value that is at least approximately five times greater than that of the plurality of inherent capacitances.Type: ApplicationFiled: December 11, 2003Publication date: July 1, 2004Inventors: Jeffrey S. Brown, David M. Fried, Edward J. Nowak, Beth Ann Rainey
-
Publication number: 20040036095Abstract: A memory cell that has first and second fully depleted transfer devices each having a body region and first and second diffused electrodes. The cell has a differential storage capacitor having at least one node abutting and in electrical contact with one of the first and second diffused electrodes of each of the transfer devices. The storage capacitor has a primary capacitance and a plurality of inherent capacitances, wherein the primary capacitance has a capaictive value that is at least approximately five times greater than that of the plurality of inherent capacitances.Type: ApplicationFiled: August 26, 2002Publication date: February 26, 2004Applicant: International Business Machines CorporationInventors: Jeffrey S. Brown, David M. Fried, Edward J. Nowak, Beth Ann Rainey
-
Patent number: 6664582Abstract: The present invention provides a memory cell and method for forming the same that results in improved cell density without overly increasing fabrication cost and complexity. The preferred embodiment of the present invention provides a fin design to form the memory cell. Specifically, a fin Field Effect Transistor (FET) is formed to provide the access transistor, and a fin capacitor is formed to provide the storage capacitor. By forming the memory cell with a fin FET and fin capacitor, the memory cell density can be greatly increased over traditional planar capacitor designs. Additionally, the memory cell can be formed with significantly less process cost and complexity than traditional deep trench capacitor designs.Type: GrantFiled: April 12, 2002Date of Patent: December 16, 2003Assignee: International Business Machines CorporationInventors: David M. Fried, Edward J. Nowak, Beth Ann Rainey
-
Publication number: 20030197194Abstract: The present invention provides a memory cell and method for forming the same that results in improved cell density without overly increasing fabrication cost and complexity. The preferred embodiment of the present invention provides a fin design to form the memory cell. Specifically, a fin Field Effect Transistor (FET) is formed to provide the access transistor, and a fin capacitor is formed to provide the storage capacitor. By forming the memory cell with a fin FET and fin capacitor, the memory cell density can be greatly increased over traditional planar capacitor designs. Additionally, the memory cell can be formed with significantly less process cost and complexity than traditional deep trench capacitor designs.Type: ApplicationFiled: April 12, 2002Publication date: October 23, 2003Applicant: International Business Machines CorporationInventors: David M. Fried, Edward J. Nowak, Beth Ann Rainey