Patents by Inventor Beth Baumert

Beth Baumert has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 10438853
    Abstract: At least one method, apparatus and system are provided for forming a hybrid oxide layer for providing for a first region of a finFET device to operate at a first voltage and a second region of the finFET to operate at a second voltage. A first set of fins are formed on an I/O device portion, and a second set of fins are formed on a core device portion of a substrate. A first and a second oxide layers are deposited on the first and second set of fins, wherein they merge to form a hybrid oxide layer. The thickness of the second oxide layer is based on a first operating voltage for the I/O device portion. The hybrid layer is removed from the core device portion such that the I/O device portion operates at the first voltage and the core device portion operates at a second voltage.
    Type: Grant
    Filed: November 22, 2017
    Date of Patent: October 8, 2019
    Assignee: GLOBALFOUNDRIES INC.
    Inventors: Shahab Siddiqui, Beth Baumert, Abu Naser M. Zainuddin, Luigi Pantisano
  • Publication number: 20190305105
    Abstract: A method for controlling the gate length within a FinFET device to increase power performance and the resulting device are provided. Embodiments include forming a vertical gate to extend over a plurality of fins; depositing a respective oxide layer over each of a plurality of skirt regions formed at respective points of intersection of the vertical gate with the plurality of fins; and oxidizing each oxide layer to form a plurality of oxidized gate skirts.
    Type: Application
    Filed: April 2, 2018
    Publication date: October 3, 2019
    Inventors: Qun GAO, Christopher NASSAR, Sugirtha KRISHNAMURTHY, Domingo Antonio FERRER LUPPI, John SPORRE, Shahab SIDDIQUI, Beth BAUMERT, Abu ZAINUDDIN, Jinping LIU, Tae Jeong LEE, Luigi PANTISANO, Heather LAZAR, Hui ZANG
  • Patent number: 10361289
    Abstract: A method of thermally oxidizing a Si fin to form an oxide layer over the Si fin and then forming an ALD oxide layer over the oxide layer and resulting device are provided. Embodiments include forming a plurality of Si fins on a Si substrate; forming a dielectric layer over the plurality of Si fins and the Si substrate; recessing the dielectric layer, exposing a top portion of the plurality of Si fins; thermally oxidizing surface of the top portion of the plurality of Si fins, an oxide layer formed; and forming an ALD oxide layer over the oxide layer.
    Type: Grant
    Filed: March 22, 2018
    Date of Patent: July 23, 2019
    Assignee: GLOBALFOUNDRIES INC.
    Inventors: Wei Zhao, Shahab Siddiqui, Haiting Wang, Ting-Hsiang Hung, Yiheng Xu, Beth Baumert, Jinping Liu, Scott Beasor, Yue Zhong, Shesh Mani Pandey
  • Publication number: 20190157157
    Abstract: At least one method, apparatus and system are provided for forming a hybrid oxide layer for providing for a first region of a finFET device to operate at a first voltage and a second region of the finFET to operate at a second voltage. A first set of fins are formed on an I/O device portion, and a second set of fins are formed on a core device portion of a substrate. A first and a second oxide layers are deposited on the first and second set of fins, wherein they merge to form a hybrid oxide layer. The thickness of the second oxide layer is based on a first operating voltage for the I/O device portion. The hybrid layer is removed from the core device portion such that the I/O device portion operates at the first voltage and the core device portion operates at a second voltage.
    Type: Application
    Filed: November 22, 2017
    Publication date: May 23, 2019
    Applicant: GLOBALFOUNDRIES INC.
    Inventors: Shahab Siddiqui, Beth Baumert, Abu Naser M. Zainuddin, Luigi Pantisano
  • Patent number: 10106892
    Abstract: Methods of forming conformal low temperature gate oxides on a HV I/O and a core logic and the resulting devices are provided. Embodiments include providing a HV I/O and core logic laterally separated on a Si substrate, each having a fin; forming a gate oxide layer over each fin and the Si substrate; forming a silicon oxy-nitride layer over the gate oxide layer; forming a sacrificial oxide layer over the silicon oxy-nitride layer; removing the sacrificial oxide and silicon oxy-nitride layers and thinning the gate oxide layer; forming a second gate oxide layer over the thinned gate oxide layer; forming a silicon oxy-nitride layer over the second gate oxide layer; removing the silicon oxy-nitride and second gate oxide layers over the core logic fin portion; forming an IL over the core logic fin portion; and forming a HfOx layer over the second silicon oxy-nitride layer and ILs.
    Type: Grant
    Filed: August 31, 2017
    Date of Patent: October 23, 2018
    Assignee: GLOBALFOUNDRIES INC.
    Inventors: Shahab Siddiqui, Abu Naser Zainuddin, Beth Baumert, Suresh Uppal
  • Publication number: 20070089740
    Abstract: A pursed lip breathing device includes a housing defining an air channel through which a user breathes. A mouthpiece is attached to the housing and includes an aperture generally aligned with the air channel so that when the user breathes through the aperture, an airflow is generated in the air channel. The mouthpiece has outer dimensions designed so that the user's lips are pursed during breathing. During breathing, the airflow in the air channel is restricted to include pressure on the user's pulmonary system. Information or feedback regarding the user's breathing may also be provided so that the user is motivated and encouraged during breathing exercises and may monitor the therapeutic effect of his or her breathing.
    Type: Application
    Filed: April 28, 2004
    Publication date: April 26, 2007
    Applicant: CHI, LLC
    Inventors: Beth Baumert, Janice Proll
  • Patent number: 7164566
    Abstract: Methods and apparatus are provided an electrostatic discharge (ESD) protection device having a first terminal and a second terminal. The ESD protection device comprises a vertical transistor having a collector coupled to the first terminal, a base, and an emitter coupled to the second terminal. A zener diode has a first terminal coupled to the first terminal of the ESD protection device and a second terminal coupled to the base of the vertical transistor. Subsurface current paths are provided to redistribute current from a surface of the vertical transistor in an ESD event. The method comprises generating an ionization current when a zener diode breaks down during an ESD event. The ionization current density from a surface zener diode region is reduced. The ionization current enables a transistor to dissipate the ESD event.
    Type: Grant
    Filed: March 19, 2004
    Date of Patent: January 16, 2007
    Assignee: Freescale Semiconductor, Inc.
    Inventors: Hongzhong Xu, Beth A. Baumert, Richard T. Ida
  • Publication number: 20050207077
    Abstract: Methods and apparatus are provided an electrostatic discharge (ESD) protection device having a first terminal and a second terminal. The ESD protection device comprises a vertical transistor having a collector coupled to the first terminal, a base, and an emitter coupled to the second terminal. A zener diode has a first terminal coupled to the first terminal of the ESD protection device and a second terminal coupled to the base of the vertical transistor. Subsurface current paths are provided to redistribute current from a surface of the vertical transistor in an ESD event. The method comprises generating an ionization current when a zener diode breaks down during an ESD event. The ionization current density from a surface zener diode region is reduced. The ionization current enables a transistor to dissipate the ESD event.
    Type: Application
    Filed: March 19, 2004
    Publication date: September 22, 2005
    Inventors: Hongzhong Xu, Beth Baumert, Richard Ida