Abstract: A process for bonding a flip chip (20), of the type having an active face provided with conductive bumps, to a substrate (22) so that its active face is oriented toward the substrate (22). The flip chip (20) is coupled through a vacuum to the distended end (32) of an ultrasonic horn (30) and then lowered onto the substrate (22) so that the bumps (20b) align with a bonding pattern on the substrate (22). A bias force is applied through the ultrasonic horn (30) to the backside of the flip chip (20), in a direction normal to the substrate (22) so that minimal lateral displacement of the flip chip (20) and the substrate (22) results. The ultrasonic horn (30) is then activated while the bias force is applied such that the ultrasonic energy is isothermally transferred in a direction normal to and across the flip chip (20) to the substrate (22) for creating a diffusion bond therebetween.

Abstract: A process for bonding a flip chip (20), of the type having an active face provided with conductive bumps, to a substrate (22) so that its active face is oriented toward the substrate (22). The flip chip (20) is coupled through a vacuum to the distended end (32) of an ultrasonic horn (30) and then lowered onto the substrate (22) so that the bumps (20b) align with a bonding pattern on the substrate (22). A bias force is applied through the ultrasonic horn (30) to the backside of the flip chip (20), in a direction normal to the substrate (22) so that minimal lateral displacement of the flip chip (20) and the substrate (22) results. The ultrasonic horn (30) is then activated while the bias force is applied such that the ultrasonic energy is isothermally transferred in a direction normal to and across the flip chip (20) to the substrate (22) for creating a diffusion bond therebetween.

Abstract: An apparatus for testing an integrated circuit includes a bond substrate having a location for an integrated circuit. The location on the bond substrate has a plurality of traces around each location. A first fixture holds the bond substrate in a fixed relation to first fixture and holds the integrated circuit in a fixed relation to the first fixture and the bond substrate. A wirebonder forms wirebonds between the traces and the bond pads. An electrical tester provides electrical signals from the traces to the bond pads to verifying the operation of the integrated circuit. A second fixture lifts the bond substrate while the integrated circuit remains held to the first fixture. A vibrator vibrates the first fixture in relation to the second fixture so that the wirebonds are broken at a predetermined location near the bond pad.

Abstract: A test apparatus for testing a know-good die integrated circuit is disclosed. The test apparatus uses conductive straps extending across trenches. The straps align with bond pads on the integrated circuit. When the bond pads are brought into contact with the straps, the straps exert a counterforce in the opposite direction to ensure a good electrical contact while testing the integrated circuit.

Abstract: A process for bonding a flip chip (20) to a substrate (22) comprising positioning the flip chip (20) above the substrate (22). The flip chip (20) has an active face provided with conductive bumps so that its active face is oriented toward the substrate (22). The flip chip (20) is placed on the substrate (22) so that the bumps align with a bonding pattern on the substrate (22). An ultrasonic horn (30) is lowered having a flat surface onto a back side of the flip chip (20). Force is applied through the ultrasonic horn (30) to the back side of the flip chip (20), which is normal to the substrate (22) so that minimal lateral displacement of the flip chip (20) and the substrate (22) results. The ultrasonic horn (30) is then activated while the force is applied so that the ultrasonic energy is isothermally transferred across the flip chip (20) to the substrate (22) and a diffusion bond is created therebetween.