Abstract: A system and method to optimize a circuit layout, and more particularly, to a system and method of post layout data preparation to optimize a circuit layout and reduce random and systematic wire and via opens and shorts. The method includes stripping existing vias in a design layout and determining design parameters of the design layout including wiring placement and dimensions. The method further includes optimizing via layout by placing vias away from edges of the wiring and adjacent vias.

Abstract: A system and method to optimize a circuit layout, and more particularly, to a system and method of post layout data preparation to optimize a circuit layout and reduce random and systematic wire and via opens and shorts. The method includes stripping existing vias in a design layout and determining design parameters of the design layout including wiring placement and dimensions. The method further includes optimizing via layout by placing vias away from edges of the wiring and adjacent vias. The invention is also directed to a design structure on which a circuit resides.

Abstract: Disclosed is a method of locating systematic defects in integrated circuits. The invention first performs a preliminary extracting and index processing of the circuit design and then performs feature searching. When performing the preliminary extracting and index processing the invention establishes a window grid for the circuit design and merges basis patterns with shapes in the circuit design within each window of the window grid. The invention transforms shapes in a each window into feature vectors by finding intersections between the basis patterns and the shapes in the windows. Then, the invention clusters the feature vectors to produce an index of feature vectors. After performing the extracting and index processing, the invention performs the process of feature searching by first identifying a defect region window of the circuit layout and similarly merging basis patterns with shapes in the defect region window. This merging process can include rotating and mirroring the shapes in the defect region.

Abstract: Disclosed is a method of locating systematic defects in integrated circuits. The invention first performs a preliminary extracting and index processing of the circuit design and then performs feature searching. When performing the preliminary extracting and index processing the invention establishes a window grid for the circuit design and merges basis patterns with shapes in the circuit design within each window of the window grid. The invention transforms shapes in a each window into feature vectors by finding intersections between the basis patterns and the shapes in the windows. Then, the invention clusters the feature vectors to produce an index of feature vectors. After performing the extracting and index processing, the invention performs the process of feature searching by first identifying a defect region window of the circuit layout and similarly merging basis patterns with shapes in the defect region window. This merging process can include rotating and mirroring the shapes in the defect region.

Abstract: Disclosed is a method of locating systematic defects in integrated circuits. The invention first performs a preliminary extracting and index processing of the circuit design and then performs feature searching. When performing the preliminary extracting and index processing the invention establishes a window grid for the circuit design and merges basis patterns with shapes in the circuit design within each window of the window grid. The invention transforms shapes in a each window into feature vectors by finding intersections between the basis patterns and the shapes in the windows. Then, the invention clusters the feature vectors to produce an index of feature vectors. After performing the extracting and index processing, the invention performs the process of feature searching by first identifying a defect region window of the circuit layout and similarly merging basis patterns with shapes in the defect region window. This merging process can include rotating and mirroring the shapes in the defect region.

Abstract: A system and method to optimize a circuit layout, and more particularly, to a system and method of post layout data preparation to optimize a circuit layout and reduce random and systematic wire and via opens and shorts. The method includes stripping existing vias in a design layout and determining design parameters of the design layout including wiring placement and dimensions. The method further includes optimizing via layout by placing vias away from edges of the wiring and adjacent vias.

Abstract: Disclosed is a method of locating systematic defects in integrated circuits. Extracting and index processing of a circuit design and feature searching are performed. During extracting and index processing, a window grid for the circuit design is established and basis patterns are merged with shapes within each. Shapes in each window are transformed into feature vectors by finding intersections between basis patterns and shapes. Feature vectors are clustered to produce an index of feature vectors. During feature searching, a defect region window of the circuit layout is identified and basis patterns are merged with shapes in the defect region window. Shapes in the defect region window are transformed into defect vectors by finding intersections between basis patterns and shapes. Feature vectors similar to the defect vector are found using representative feature vectors from the index of feature vectors. Similarities and differences between defect vectors and feature vectors are analyzed.

Abstract: A system, method and media for locating and defining process sensitive sites isolated to specific geometries or shape configurations within chip design data. Once a systemic process sensitive site is identified, a 3D design checking deck is coded and executed through a design checker on physical design data. Target match shapes are produced and embedded back into the design data. Pictures, maps and coordinates of process sensitive sites are produced and sent to a website library for reference.

Abstract: A trough adjusted optical proximity correction for vias which takes into account the topography on a wafer created by prior processing. The vias are classified into one of two groups, coincident vias which have an edge coincident with an edge of the trough, and noncoincident vias which do not have an edge coincident with an edge of the trough, by analyzing the via and trough designs. Any coincident via is marked as valid for an optical proximity correction (OPC). Any noncoincident via is marked invalid for OPC. OPC is then performed to the via level. Only vias marked as valid for OPC will keep the correction. All other vias will keep their original design size. Alternatively, coincident vias can be simply treated differently from noncoincident vias. For instance, coincident vias can be subjected to an aggressive OPC correction, while noncoincident vias are subjected to a less aggressive OPC correction.

Abstract: A system, method and media for locating and defining process sensitive sites isolated to specific geometries or shape configurations within chip design data. Once a systemic process sensitive site is identified, a 3D design checking deck is coded and executed through a design checker on physical design data. Target match shapes are produced and embedded back into the design data. Pictures, maps and coordinates of process sensitive sites are produced and sent to a website library for reference.

Abstract: A trough adjusted optical proximity correction for vias which takes into account the topography on a wafer created by prior processing. The vias are classified into one of two groups, coincident vias which have an edge coincident with an edge of the trough, and noncoincident vias which do not have an edge coincident with an edge of the trough, by analyzing the via and trough designs. Any coincident via is marked as valid for an optical proximity correction (OPC). Any noncoincident via is marked invalid for OPC. OPC is then performed to the via level. Only vias marked as valid for OPC will keep the correction. All other vias will keep their original design size. Alternatively, coincident vias can be simply treated differently from noncoincident vias. For instance, coincident vias can be subjected to an aggressive OPC correction, while noncoincident vias are subjected to a less aggressive OPC correction.

Abstract: A method and structure for a semiconductor chip includes a plurality of layers of interconnect metallurgy, at least one layer of deformable dielectric material over the interconnect metallurgy, at least one input/output bonding pad, and a support structure that includes a substantially rigid dielectric in a supporting relationship to the pad that avoids crushing the deformable dielectric material.