Patents by Inventor Bettina Nechay
Bettina Nechay has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 10854600Abstract: A method of forming an integrated circuit can include forming a heterostructure over a substrate structure, wherein the given substrate structure comprises a given semiconductor material. The method can include etching a castellated channel region in an e-mode device area of the heterostructure that defines a plurality of ridge channels interleaved between a plurality of trenches, the ridge channels comprising another semiconductor material. The method can also include forming an isolation region on the heterostructure to electrically isolate the e-mode device area from a d-mode device area of the heterostructure. The method can further include forming a mask with an opening that defines a castellated gate opening overlying the castellated channel region and the mask defines an opening overlaying a single planar gate overlying the d-mode device area of the heterostructure. The method can also include performing a contact fill with conductive material to form a castellated gate contact.Type: GrantFiled: September 20, 2019Date of Patent: December 1, 2020Assignee: NORTHROP GRUMMAN SYSTEMS CORPORATIONInventors: Justin Andrew Parke, Eric J. Stewart, Robert S. Howell, Howell George Henry, Bettina Nechay, Harlan Carl Cramer, Matthew Russell King, Shalini Gupta, Ronald G. Freitag, Karen Marie Renaldo
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Patent number: 10629767Abstract: An integrated circuit includes a substrate material that includes an epitaxial layer, wherein the substrate material and the epitaxial layer form a first semiconductor material with the epitaxial layer having a first conductivity type. At least one nanowire comprising a second semiconductor material having a second conductivity type doped differently than the first conductivity type of the first semiconductor material forms a junction crossing region with the first semiconductor material. The nanowire and the first semiconductor material form an avalanche photodiode (APD) in the junction crossing region to enable single photon detection. In an alternative configuration, the APD is formed as a p-i-n crossing region where n represents an n-type material, i represents an intrinsic layer, and p represents a p-type material.Type: GrantFiled: December 27, 2018Date of Patent: April 21, 2020Assignee: NORTHROP GRUMMAN SYSTEMS CORPORATIONInventors: Narsingh B. Singh, John V. Veliadis, Bettina Nechay, Andre Berghmans, David J. Knuteson, David Kahler, Brian Wagner, Marc Sherwin
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Publication number: 20200013775Abstract: A method of forming an integrated circuit can include forming a heterostructure over a substrate structure, wherein the given substrate structure comprises a given semiconductor material. The method can include etching a castellated channel region in an e-mode device area of the heterostructure that defines a plurality of ridge channels interleaved between a plurality of trenches, the ridge channels comprising another semiconductor material. The method can also include forming an isolation region on the heterostructure to electrically isolate the e-mode device area from a d-mode device area of the heterostructure. The method can further include forming a mask with an opening that defines a castellated gate opening overlying the castellated channel region and the mask defines an opening overlaying a single planar gate overlying the d-mode device area of the heterostructure. The method can also include performing a contact fill with conductive material to form a castellated gate contact.Type: ApplicationFiled: September 20, 2019Publication date: January 9, 2020Applicant: NORTHROP GRUMMAN SYSTEMS CORPORATIONInventors: JUSTIN ANDREW PARKE, ERIC J. STEWART, ROBERT S. HOWELL, HOWELL GEORGE HENRY, BETTINA NECHAY, HARLAN CARL CRAMER, MATTHEW RUSSELL KING, SHALINI GUPTA, RONALD G. FREITAG, KAREN MARIE RENALDO
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Patent number: 10468406Abstract: A circuit is provided that includes a castellated channel device that comprises a heterostructure overlying a substrate structure, a castellated channel device area formed in the heterostructure that defines a plurality of ridge channels interleaved between a plurality of trenches, and a three-sided castellated conductive gate contact that extends across the castellated channel device area. The three-sided gate contact substantially surrounds each ridge channel around their tops and their sides to overlap a channel interface of heterostructure of each of the plurality of ridge channels. The three-sided castellated conductive gate contact extends along at least a portion of a length of each ridge channel.Type: GrantFiled: October 8, 2014Date of Patent: November 5, 2019Assignee: NORTHROP GRUMMAN SYSTEMS CORPORATIONInventors: Justin Andrew Parke, Eric J. Stewart, Robert S. Howell, Howell George Henry, Bettina Nechay, Harlan Carl Cramer, Matthew Russell King, Shalini Gupta, Ronald G. Freitag, Karen Marie Renaldo
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Publication number: 20190131480Abstract: An integrated circuit includes a substrate material that includes an epitaxial layer, wherein the substrate material and the epitaxial layer form a first semiconductor material with the epitaxial layer having a first conductivity type. At least one nanowire comprising a second semiconductor material having a second conductivity type doped differently than the first conductivity type of the first semiconductor material forms a junction crossing region with the first semiconductor material. The nanowire and the first semiconductor material form an avalanche photodiode (APD) in the junction crossing region to enable single photon detection. In an alternative configuration, the APD is formed as a p-i-n crossing region where n represents an n-type material, i represents an intrinsic layer, and p represents a p-type material.Type: ApplicationFiled: December 27, 2018Publication date: May 2, 2019Applicant: NORTHROP GRUMMAN SYSTEMS CORPORATIONInventors: NARSINGH B. SINGH, JOHN V. VELIADIS, BETTINA NECHAY, ANDRE BERGHMANS, DAVID J. KNUTESON, DAVID KAHLER, BRIAN WAGNER, MARC SHERWIN
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Patent number: 10211359Abstract: An integrated circuit includes a substrate material that includes an epitaxial layer, wherein the substrate material and the epitaxial layer form a first semiconductor material with the epitaxial layer having a first conductivity type. At least one nanowire comprising a second semiconductor material having a second conductivity type doped differently than the first conductivity type of the first semiconductor material forms a junction crossing region with the first semiconductor material. The nanowire and the first semiconductor material form an avalanche photodiode (APD) in the junction crossing region to enable single photon detection. In an alternative configuration, the APD is formed as a p-i-n crossing region where n represents an n-type material, i represents an intrinsic layer, and p represents a p-type material.Type: GrantFiled: November 18, 2016Date of Patent: February 19, 2019Assignee: Northrop Grumman Systems CorporationInventors: Narsingh B. Singh, John V. Veliadis, Bettina Nechay, Andre Berghmans, David J. Knuteson, David Kahler, Brian Wagner, Marc Sherwin
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Patent number: 10084075Abstract: A transistor device is provided that comprises a base structure, and a superlattice structure overlying the base structure and comprising a multichannel ridge having sloping sidewalls. The multichannel ridge comprises a plurality of heterostructures that each form a channel of the multichannel ridge, wherein a parameter of at least one of the heterostructures is varied relative to other heterostructures of the plurality of heterostructures. The transistor device further comprises a three-sided gate contact that wraps around and substantially surrounds the top and sides of the multichannel ridge along at least a portion of its depth.Type: GrantFiled: June 15, 2017Date of Patent: September 25, 2018Assignee: Northrop Grumman Systems CorporationInventors: Bettina A. Nechay, Shalini Gupta, Matthew Russell King, Eric J. Stewart, Robert S. Howell, Justin Andrew Parke, Harlan Carl Cramer, Howell George Henry, Ronald G. Freitag, Karen Marie Renaldo
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Publication number: 20170288045Abstract: A transistor device is provided that comprises a base structure, and a superlattice structure overlying the base structure and comprising a multichannel ridge having sloping sidewalls. The multichannel ridge comprises a plurality of heterostructures that each form a channel of the multichannel ridge, wherein a parameter of at least one of the heterostructures is varied relative to other heterostructures of the plurality of heterostructures. The transistor device further comprises a three-sided gate contact that wraps around and substantially surrounds the top and sides of the multichannel ridge along at least a portion of its depth.Type: ApplicationFiled: June 15, 2017Publication date: October 5, 2017Applicant: NORTHROP GRUMMAN SYSTEMS CORPORATIONInventors: BETTINA A. NECHAY, SHALINI GUPTA, MATTHEW RUSSELL KING, ERIC J. STEWART, ROBERT S. HOWELL, JUSTIN ANDREW PARKE, HARLAN CARL CRAMER, HOWELL GEORGE HENRY, RONALD G. FREITAG, KAREN MARIE RENALDO
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Patent number: 9773897Abstract: A transistor device is provided that includes a base structure and a superlattice structure that overlies the base structure. The superlattice structure comprises a multichannel ridge having sides that extend to the base structure. The multichannel ridge comprises a plurality of heterostructures that each form a channel of the multichannel ridge. A three-sided gate configuration is provided that wraps around and substantially surrounds the top and sides of the multichannel ridge along at least a portion of its depth. The three-sided gate configuration is configured to re-distribute peak electric fields along the three-sided gate configuration to facilitate the increase in breakdown voltage of the transistor device.Type: GrantFiled: April 1, 2015Date of Patent: September 26, 2017Assignee: Northrop Grumman Systems CorporationInventors: Bettina A. Nechay, Robert S. Howell, Eric J. Stewart, Howell George Henry, Justin Andrew Parke, Ronald G. Freitag
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Patent number: 9711616Abstract: A dual-channel field effect transistor (FET) device having increased amplifier linearity and a method of manufacturing same are disclosed. In an embodiment, the device includes a channel layer having a top surface and provided within a channel between a source electrode and a drain electrode. A barrier layer is formed on the channel layer in alternating first and second barrier thicknesses along the channel. The first barrier thicknesses form thinner regions and the second barrier thicknesses form thicker regions. A gate electrode is deposited on the barrier layer. The thinner regions have a first pinch-off voltage and the thicker regions have a larger second pinch-off voltage, such that the thinner and thicker regions are configured to turn on at different points on a drain current-gate voltage transfer curve. Transfer curve linearity is increased as a function of the gate voltage.Type: GrantFiled: December 23, 2014Date of Patent: July 18, 2017Assignee: NORTHROP GRUMMAN SYSTEMS CORPORATIONInventors: Eric J. Stewart, Bettina A. Nechay, Karen M. Renaldo, Howell G. Henry, Ronald G. Freitag
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Patent number: 9711615Abstract: A transistor device is provided that comprises a base structure, and a superlattice structure overlying the base structure and comprising a multichannel ridge having sloping sidewalls. The multichannel ridge comprises a plurality of heterostructures that each form a channel of the multichannel ridge, wherein a parameter of at least one of the heterostructures is varied relative to other heterostructures of the plurality of heterostructures. The transistor device further comprises a three-sided gate contact that wraps around and substantially surrounds the top and sides of the multichannel ridge along at least a portion of its depth.Type: GrantFiled: July 28, 2016Date of Patent: July 18, 2017Assignee: Northrop Grumman Systems CorporationInventors: Bettina A. Nechay, Shalini Gupta, Matthew Russell King, Eric J. Stewart, Robert S. Howell, Justin Andrew Parke, Harlan Carl Cramer, Howell George Henry, Ronald G. Freitag, Karen Marie Renaldo
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Publication number: 20170194527Abstract: An integrated circuit includes a substrate material that includes an epitaxial layer, wherein the substrate material and the epitaxial layer form a first semiconductor material with the epitaxial layer having a first conductivity type. At least one nanowire comprising a second semiconductor material having a second conductivity type doped differently than the first conductivity type of the first semiconductor material forms a junction crossing region with the first semiconductor material. The nanowire and the first semiconductor material form an avalanche photodiode (APD) in the junction crossing region to enable single photon detection. In an alternative configuration, the APD is formed as a p-i-n crossing region where n represents an n-type material, i represents an intrinsic layer, and p represents a p-type material.Type: ApplicationFiled: November 18, 2016Publication date: July 6, 2017Applicant: NORTHROP GRUMMAN SYSTEMS CORPORATIONInventors: NARSINGH B. SINGH, JOHN V. VELIADIS, BETTINA NECHAY, ANDRE BERGHMANS, DAVID J. KNUTESON, DAVID KAHLER, BRIAN WAGNER, MARC SHERWIN
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Patent number: 9570646Abstract: An integrated circuit includes a substrate material that includes an epitaxial layer, wherein the substrate material and the epitaxial layer form a first semiconductor material with the epitaxial layer having a first conductivity type. At least one nanowire comprising a second semiconductor material having a second conductivity type doped differently than the first conductivity type of the first semiconductor material forms a junction crossing region with the first semiconductor material. The nanowire and the first semiconductor material form an avalanche photodiode (APD) in the junction crossing region to enable single photon detection. In an alternative configuration, the APD is formed as a p-i-n crossing region where n represents an n-type material, i represents an intrinsic layer, and p represents a p-type material.Type: GrantFiled: February 20, 2014Date of Patent: February 14, 2017Assignee: Northrop Grumman Systems CorporationInventors: Narsingh B. Singh, John V. Veliadis, Bettina Nechay, Andre Berghmans, David J. Knuteson, David Kahler, Brian Wagner, Marc Sherwin
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Publication number: 20160336425Abstract: A transistor device is provided that comprises a base structure, and a superlattice structure overlying the base structure and comprising a multichannel ridge having sloping sidewalls. The multichannel ridge comprises a plurality of heterostructures that each form a channel of the multichannel ridge, wherein a parameter of at least one of the heterostructures is varied relative to other heterostructures of the plurality of heterostructures. The transistor device further comprises a three-sided gate contact that wraps around and substantially surrounds the top and sides of the multichannel ridge along at least a portion of its depth.Type: ApplicationFiled: July 28, 2016Publication date: November 17, 2016Applicant: NORTHROP GRUMMAN SYSTEMS CORPORATIONInventors: BETTINA A. NECHAY, SHALINI GUPTA, MATTHEW RUSSELL KING, ERIC J. STEWART, ROBERT S. HOWELL, JUSTIN ANDREW PARKE, HARLAN CARL CRAMER, HOWELL GEORGE HENRY, RONALD G. FREITAG, KAREN MARIE RENALDO
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Patent number: 9472634Abstract: A device is provided that comprises a first pillar disposed in a first region and overlying a base structure, and a second pillar disposed in a second region and overlying the base structure and being spaced apart from the first pillar by a device region. A bridge is disposed in the device region with a first end connected to the first pillar and a second end connected to the second pillar. The bridge includes a top, sides, and a bottom. The bridge is formed from one or more heterostructures with an undercut opening extending from the bottom to an underlying structure. A four-sided conductive contact wraps around and substantially surrounds the bridge around its top, its sides, and its bottom along at least a portion of its length between the first and second end.Type: GrantFiled: March 9, 2016Date of Patent: October 18, 2016Assignee: Northrop Grumman Systems CorporationInventors: Eric J Stewart, Howell George Henry, Robert S. Howell, Matthew Russell King, Justin Andrew Parke, Bettina Nechay, Harlan Carl Cramer, Ronald G Freitag, Karen Marie Renaldo
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Patent number: 9466679Abstract: A device is provided that comprises a first pillar disposed in a first region and overlying a base structure, and a second pillar disposed in a second region and overlying the base structure and being spaced apart from the first pillar by a device region. A bridge is disposed in the device region with a first end connected to the first pillar and a second end connected to the second pillar. The bridge includes a top, sides, and a bottom. The bridge is formed from one or more heterostructures with an undercut opening extending from the bottom to an underlying structure. A four-sided conductive contact wraps around and substantially surrounds the bridge around its top, its sides, and its bottom along at least a portion of its length between the first and second end.Type: GrantFiled: August 13, 2014Date of Patent: October 11, 2016Assignee: Northrop Grumman Systems CorporationInventors: Eric J. Stewart, Howell George Henry, Robert S. Howell, Matthew Russell King, Justin Andrew Parke, Bettina Nechay, Harlan Carl Cramer, Karen Marie Renaldo, Ronald G. Freitag
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Publication number: 20160293713Abstract: A transistor device is provided that includes a base structure and a superlattice structure that overlies the base structure. The superlattice structure comprises a multichannel ridge having sides that extend to the base structure. The multichannel ridge comprises a plurality of heterostructures that each form a channel of the multichannel ridge. A three-sided gate configuration is provided that wraps around and substantially surrounds the top and sides of the multichannel ridge along at least a portion of its depth. The three-sided gate configuration is configured to re-distribute peak electric fields along the three-sided gate configuration to facilitate the increase in breakdown voltage of the transistor device.Type: ApplicationFiled: April 1, 2015Publication date: October 6, 2016Applicant: NORTHROP GRUMMAN SYSTEMS CORPORATIONInventors: BETTINA A. NECHAY, Robert S. Howell, Eric J. Stewart, Howell George Henry, Justin Andrew Parke, Ronald G. Freitag
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Patent number: 9419120Abstract: A transistor device is provided that comprises a base structure, and a superlattice structure overlying the base structure and comprising a multichannel ridge having sloping sidewalls. The multichannel ridge comprises a plurality of heterostructures that each form a channel of the multichannel ridge, wherein a parameter of at least one of the heterostructures is varied relative to other heterostructures of the plurality of heterostructures. The transistor device further comprises a three-sided gate contact that wraps around and substantially surrounds the top and sides of the multichannel ridge along at least a portion of its depth.Type: GrantFiled: November 5, 2014Date of Patent: August 16, 2016Assignee: Northrop Grumman Systems CorporationInventors: Bettina A. Nechay, Shalini Gupta, Matthew Russell King, Eric J. Stewart, Robert S. Howell, Justin Andrew Parke, Harlan Carl Cramer, Howell George Henry, Ronald G. Freitag, Karen Marie Renaldo
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Publication number: 20160190267Abstract: A device is provided that comprises a first pillar disposed in a first region and overlying a base structure, and a second pillar disposed in a second region and overlying the base structure and being spaced apart from the first pillar by a device region. A bridge is disposed in the device region with a first end connected to the first pillar and a second end connected to the second pillar. The bridge includes a top, sides, and a bottom. The bridge is formed from one or more heterostructures with an undercut opening extending from the bottom to an underlying structure. A four-sided conductive contact wraps around and substantially surrounds the bridge around its top, its sides, and its bottom along at least a portion of its length between the first and second end.Type: ApplicationFiled: March 9, 2016Publication date: June 30, 2016Applicant: NORTHROP GRUMMAN SYSTEMS CORPORATIONInventors: ERIC J. STEWART, HOWELL GEORGE HENRY, ROBERT S. HOWELL, MATTHEW RUSSELL KING, JUSTIN ANDREW PARKE, BETTINA NECHAY, HARLAN CARL CRAMER, RONALD G. FREITAG, KAREN MARIE RENALDO
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Publication number: 20160181364Abstract: A dual-channel field effect transistor (FET) device having increased amplifier linearity and a method of manufacturing same are disclosed. In an embodiment, the device includes a channel layer having a top surface and provided within a channel between a source electrode and a drain electrode. A barrier layer is formed on the channel layer in alternating first and second barrier thicknesses along the channel. The first barrier thicknesses form thinner regions and the second barrier thicknesses form thicker regions. A gate electrode is deposited on the barrier layer. The thinner regions have a first pinch-off voltage and the thicker regions have a larger second pinch-off voltage, such that the thinner and thicker regions are configured to turn on at different points on a drain current-gate voltage transfer curve. Transfer curve linearity is increased as a function of the gate voltage.Type: ApplicationFiled: December 23, 2014Publication date: June 23, 2016Inventors: Eric J. Stewart, Bettina A. Nechay, Karen M. Renaldo, Howell G. Henry, Ronald G. Freitag