Abstract: A clock domain crossing can occur earlier in time by detection of when a data signal will coincide with a TSV (time slot valid) signal but the valid signal associated with the data signal will not coincide with a TSV. In response to such a detection, the domain crossing circuit can send the valid signal early, resulting in a valid signal sent on an earlier TSV and the data signal sent on a TSV. In one embodiment, such a system can cause a data signal to be received in a slower clock domain on a first edge of the slower clock signal after the data is queued in the faster clock domain. The sending of the early valid indication can reduce latency in transferring data between clock domains.

Abstract: A method is described. The method includes periodically maintaining memory devices with circuitry of a memory controller. The circuitry is to act in response to signals from timer and scheduling circuitry that determine when memory maintenance is to occur to which of the memory devices. The periodically maintaining is performed while the memory controller is able to perform read/write operations from/to the memory devices. The method also includes placing the memory controller into a sleep mode in which the memory controller is not able to read/write from/to the memory devices, where, the periodically maintaining continues to be performed while the memory controller is within the sleep mode.

Abstract: A clock domain crossing can occur earlier in time by detection of when a data signal will coincide with a TSV (time slot valid) signal but the valid signal associated with the data signal will not coincide with a TSV. In response to such a detection, the domain crossing circuit can send the valid signal early, resulting in a valid signal sent on an earlier TSV and the data signal sent on a TSV. In one embodiment, such a system can cause a data signal to be received in a slower clock domain on a first edge of the slower clock signal after the data is queued in the faster clock domain. The sending of the early valid indication can reduce latency in transferring data between clock domains.