Abstract: A semiconductor memory device includes an alternating stack of insulating layers and electrically conductive layers, a memory opening vertically extending through the alternating stack, and a memory opening fill structure located in the memory opening and including a vertical stack of discrete ferroelectric material portions and a vertical semiconductor channel. In one embodiment, the discrete ferroelectric material portions include a ferroelectric alloy material of a first dielectric metal oxide material and a second dielectric metal oxide material. In another embodiment, each of the discrete ferroelectric material portions is oxygen-deficient.

Abstract: A semiconductor memory device includes an alternating stack of insulating layers and electrically conductive layers, a memory opening vertically extending through the alternating stack, and a memory opening fill structure located in the memory opening and including a vertical stack of discrete ferroelectric material portions and a vertical semiconductor channel. In one embodiment, the discrete ferroelectric material portions include a ferroelectric alloy material of a first dielectric metal oxide material and a second dielectric metal oxide material. In another embodiment, each of the discrete ferroelectric material portions is oxygen-deficient.

Abstract: A magnetoelectric memory device includes a magnetic tunnel junction located between a first electrode and a second electrode. The magnetic tunnel junction includes a reference layer, a nonmagnetic tunnel barrier layer, a free layer, and a dielectric capping layer. At least one layer that provides voltage-controlled magnetic anisotropy is provided within the magnetic tunnel junction, which may include a pair of nonmagnetic metal dust layers located on, or within, the free layer, or a two-dimensional metal compound layer including a compound of a nonmagnetic metallic element and a nonmetallic element.

Abstract: A magnetoelectric memory device includes a magnetic tunnel junction located between a first electrode and a second electrode. The magnetic tunnel junction includes a reference layer, a nonmagnetic tunnel barrier layer, a free layer, and a dielectric capping layer. At least one layer that provides voltage-controlled magnetic anisotropy is provided within the magnetic tunnel junction, which may include a pair of nonmagnetic metal dust layers located on, or within, the free layer, or a two-dimensional metal compound layer including a compound of a nonmagnetic metallic element and a nonmetallic element.

Abstract: A magnetoelectric memory device includes a magnetic tunnel junction located between a first electrode and a second electrode. The magnetic tunnel junction includes a reference layer, a nonmagnetic tunnel barrier layer, a free layer, and a dielectric capping layer. At least one layer that provides voltage-controlled magnetic anisotropy is provided within the magnetic tunnel junction, which may include a pair of nonmagnetic metal dust layers located on, or within, the free layer, or a two-dimensional metal compound layer including a compound of a nonmagnetic metallic element and a nonmetallic element.

Abstract: Magnetoelectric or magnetoresistive memory cells may include a plurality of reference layers and optionally a plurality of free layers to enhance the tunneling magnetoresistance (TMR) ratio.

Abstract: A magnetoresistive memory cell includes a first terminal electrode, a second terminal electrode, and a magnetoresistive layer stack located between the first terminal electrode and the second terminal electrode and including, from one side to another, a reference layer, a dielectric tunnel barrier layer, a free layer, and a material layer having two different states of lattice deformation which have different average in-plane lattice constants and which are configured to apply different in-plane stress. The material layer may be a metal-insulator transition (MIT) material layer that exhibits a phase transition between an insulator state and a metal state.

Abstract: A magnetic tunnel junction may include a platinum-containing layer including at least one of Ir, Hf or Ru in contact with a free layer, or a combination of a platinum layer and a Hf or Ir layer formed on opposite sides of a free layer.

Abstract: A ferroelectric transistor includes a semiconductor channel comprising a semiconductor material, a strained and/or defect containing ferroelectric gate dielectric layer located on a surface of the semiconductor channel, a source region located on a first end portion of the semiconductor channel, and a drain region located on a second end portion of the semiconductor channel.

Abstract: A magnetoelectric memory device includes a magnetic tunnel junction located between a first electrode and a second electrode. The magnetic tunnel junction includes a reference layer, a nonmagnetic tunnel barrier layer, a free layer, and a dielectric capping layer. At least one layer that provides voltage-controlled magnetic anisotropy is provided within the magnetic tunnel junction, which may include a pair of nonmagnetic metal dust layers located on, or within, the free layer, or a two-dimensional metal compound layer including a compound of a nonmagnetic metallic element and a nonmetallic element.

Abstract: A magnetoelectric memory device includes a magnetic tunnel junction located between a first electrode and a second electrode. The magnetic tunnel junction includes a reference layer, a nonmagnetic tunnel barrier layer, a free layer, and a dielectric capping layer. At least one layer that provides voltage-controlled magnetic anisotropy is provided within the magnetic tunnel junction, which may include a pair of nonmagnetic metal dust layers located on, or within, the free layer, or a two-dimensional metal compound layer including a compound of a nonmagnetic metallic element and a nonmetallic element.

Abstract: A magnetoelectric memory device includes a magnetic tunnel junction located between a first electrode and a second electrode. The magnetic tunnel junction includes a reference layer, a nonmagnetic tunnel barrier layer, a free layer, and a dielectric capping layer. At least one layer that provides voltage-controlled magnetic anisotropy is provided within the magnetic tunnel junction, which may include a pair of nonmagnetic metal dust layers located on, or within, the free layer, or a two-dimensional metal compound layer including a compound of a nonmagnetic metallic element and a nonmetallic element.

Abstract: An antiferroelectric memory device includes at least one antiferroelectric memory cell. Each of the at least one antiferroelectric memory cell includes a first electrode, a second electrode and a stack containing an antiferroelectric layer and a doped semiconductor layer or a ferroelectric layer located between the first and the second electrodes.

Abstract: A magnetoresistive memory device includes a first electrode, a second electrode that is spaced from the first electrode, and a perpendicular magnetic tunnel junction layer stack located between the first electrode and the second electrode. The perpendicular magnetic tunnel junction layer stack includes, from one side to another: a reference layer having a fixed reference magnetization direction, a first spinel layer located including a first polycrystalline spinel material having (001) texture along an axial direction that is perpendicular to an interface with the reference layer, a magnesium oxide layer including a polycrystalline magnesium oxide material having (001) texture along the axial direction, a second spinel layer including a second polycrystalline spinel material having (001) texture along the axial direction, and a ferromagnetic free layer.

Abstract: An antiferroelectric memory device includes at least one antiferroelectric memory cell. Each of the at least one antiferroelectric memory cell includes a first electrode, a second electrode and a stack containing an antiferroelectric layer and a doped semiconductor layer or a ferroelectric layer located between the first and the second electrodes.

Abstract: A magnetoresistive memory device includes a magnetic tunnel junction including a free layer, at least two tunneling dielectric barrier layers, and at least one metallic quantum well layer. The quantum well layer leads to the resonant electron tunneling through the magnetic tunnel junction in such a way that it strongly enhances the tunneling probability for one of the magnetization states of the free layer, while this tunneling probability remains much smaller in the opposite magnetization state of the free layer. The device can be configured in a spin transfer torque device configuration, a voltage-controlled magnetic anisotropy, a voltage controlled exchange coupling device configuration, or a spin-orbit-torque device configuration.

Abstract: A magnetoresistive memory device includes a magnetic tunnel junction including a free layer, at least two tunneling dielectric barrier layers, and at least one metallic quantum well layer. The quantum well layer leads to the resonant electron tunneling through the magnetic tunnel junction in such a way that it strongly enhances the tunneling probability for one of the magnetization states of the free layer, while this tunneling probability remains much smaller in the opposite magnetization state of the free layer. The device can be configured in a spin transfer torque device configuration, a voltage-controlled magnetic anisotropy, a voltage controlled exchange coupling device configuration, or a spin-orbit-torque device configuration.

Abstract: Magnetoelectric or magnetoresistive memory cells include a magnesium containing nonmagnetic metal dust layer located between a free layer and a dielectric capping layer.

Abstract: Magnetoelectric or magnetoresistive memory cells include a magnesium containing nonmagnetic metal dust layer located between a free layer and a dielectric capping layer.

Abstract: A memory device includes a first electrode, a second electrode that is spaced from the first electrode, a fixed vertical magnetization structure configured to generate a fixed vertical magnetic field and located between the first electrode and the second electrode, at least one layer stack located between the fixed magnetization structure and the second electrode and containing respective spacer dielectric layer and a respective additional reference layer including a respective ferromagnetic material having perpendicular magnetic anisotropy, and a magnetic tunnel junction located between the at least one layer stack and the second electrode, the magnetic tunnel junction containing a reference layer, a free layer, and a nonmagnetic tunnel barrier layer located between the reference layer and the free layer, and the reference layer being more proximal to the at least one layer stack than the free layer is to the at least one layer stack.