Abstract: A switched capacitor parasitic insensitive integrator comprises an operational amplifier (6), an integrating capacitor C.sub.2, a switched capacitor C, and four switches, two of even phase E1, E2 and two of odd phase 01, 02. In order to minimize the effect of capacitances (42) associated with the switches a 4-phase switching waveform is used such that E2 opens before E1, 02 opens before 01, E1 is not closed when 01 is closed and E2 is not closed when 02 is closed. A clock circuit may be used to provide the appropriate 4-phase switching waveform with a separate phase signal to each switch or a 2-phase switching waveform may be used with one phase signal to the E switches and the other phase signal to the O switches and the two switches E2, 02 biassed relative to E1, 01 such that the required differences in switching times occur.