Abstract: An arithmetic processor includes an input buffer and a result buffer connected through a pair of multiplexers to a pair of working registers feeding three parallel execution units. Operands stored in the buffers are selected for processing by addressing the buffers and multiplexers. Instruction overlapping is provided whereby operands of one instruction are read in parallel with the execution of the previous instruction. Further, reverse operations are processed identically as forward or normal operations except for addressing thereby achieving invarience of performance under non-communicative instructions.

Abstract: In a high speed arithmetic apparatus, the tally coded output of a modular mask generator addressed by a binary first operand and the tally coded input of a priority encoder are joined together by an interconnecting apparatus. The interconnecting apparatus is responsive in form to a second operand and to a selected arithmetic operation to provide at the output of the priority encoder the binary resultant of the selected operation executed upon the first and second operands. The interconnecting apparatus is disclosed in its simplest embodiment as fixed hardwired connections and in its most sophisticated embodiment as a dynamically microprogrammable full crossbar network.

Abstract: A high speed modular masking circuit having utility in field extraction, bit checking, and other like operations includes a plurality of input address lines for receiving binary numerical representations, two control lines, and a plurality of output masking lines, the number of output lines being equal in number to two raised in power to the number of input lines. When both control lines are at the same binary logic level, that level is likewise present on all output lines. When otherwise, a number of contiguous ones or zeroes are present on the output lines starting at the first output line, the number of ones or zeroes being equal to the binary numerical representation present at the input address lines and the number being either ones or zeroes depending upon the logic levels present on the control lines. The modular masking circuit is adaptable to various embodiments suitable for SSI, MSI, and LSI.