Patents by Inventor Bhanu Jaiswal

Bhanu Jaiswal has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Nanowires coated on traces in electronic devices
    Patent number: 9627320
    Abstract: Methods and devices including the formation of a layer of nanowires on wiring line traces are described. One device comprises a first dielectric layer and a plurality of traces on the first dielectric layer, the traces comprising Cu. The traces include a layer of ZnO nanowires positioned thereon. A second dielectric layer is positioned on the first dielectric layer and on the traces, wherein the second dielectric layer is in direct contact with the ZnO nanowires. Other embodiments are described and claimed.
    Type: Grant
    Filed: December 23, 2011
    Date of Patent: April 18, 2017
    Assignee: INTEL CORPORATION
    Inventors: Rahul Panat, Bhanu Jaiswal
  • Mechanism for facilitating and employing a magnetic grid array
    Patent number: 9461431
    Abstract: A mechanism is described for facilitating and employing a magnetic grid array according to one embodiment. A method of embodiments may include engaging, via magnetic force of a magnet, magnetic contacts of a magnetic grid array to substrate lands of a package substrate of an integrated circuit package of a computing system, and disengaging, via a removal lever, the magnetic contacts from the substrate lands.
    Type: Grant
    Filed: June 26, 2015
    Date of Patent: October 4, 2016
    Assignee: Intel Corporation
    Inventors: Gregorio R. Murtagian, Bhanu Jaiswal, Sriram Srinivasan, Michael J. Hill
  • MECHANISM FOR FACILITATING AND EMPLOYING A MAGNETIC GRID ARRAY
    Publication number: 20150318655
    Abstract: A mechanism is described for facilitating and employing a magnetic grid array according to one embodiment. A method of embodiments may include engaging, via magnetic force of a magnet, magnetic contacts of a magnetic grid array to substrate lands of a package substrate of an integrated circuit package of a computing system, and disengaging, via a removal lever, the magnetic contacts from the substrate lands.
    Type: Application
    Filed: June 26, 2015
    Publication date: November 5, 2015
    Applicant: INTEL CORPORATION
    Inventors: GREGORIO R. MURTAGIAN, BHANU JAISWAL, SRIRAM SRINIVASAN, MICHAEL J. HILL
  • Mechanism for facilitating and employing a magnetic grid array
    Patent number: 9118143
    Abstract: A mechanism is described for facilitating and employing a magnetic grid array according to one embodiment. A method of embodiments may include engaging, via magnetic force of a magnet, magnetic contacts of a magnetic grid array to substrate lands of a package substrate of an integrated circuit package of a computing system, and disengaging, via a removal lever, the magnetic contacts from the substrate lands.
    Type: Grant
    Filed: December 28, 2012
    Date of Patent: August 25, 2015
    Assignee: Intel Corporation
    Inventors: Gregorio R. Murtagian, Bhanu Jaiswal, Sriram Srinivasan, Michael J. Hill
  • NANOWIRES COATED ON TRACES IN ELECTRONIC DEVICES
    Publication number: 20150048508
    Abstract: Methods and devices including the formation of a layer of nanowires on wiring line traces are described. One device comprises a first dielectric layer and a plurality of traces on the first dielectric layer, the traces comprising Cu. The traces include a layer of ZnO nanowires positioned thereon. A second dielectric layer is positioned on the first dielectric layer and on the traces, wherein the second dielectric layer is in direct contact with the ZnO nanowires. Other embodiments are described and claimed.
    Type: Application
    Filed: December 23, 2011
    Publication date: February 19, 2015
    Inventors: Rahul Panat, Bhanu Jaiswal
  • MECHANISM FOR FACILITATING AND EMPLOYING A MAGNETIC GRID ARRAY
    Publication number: 20140187057
    Abstract: A mechanism is described for facilitating and employing a magnetic grid array according to one embodiment. A method of embodiments may include engaging, via magnetic force of a magnet, magnetic contacts of a magnetic grid array to substrate lands of a package substrate of an integrated circuit package of a computing system, and disengaging, via a removal lever, the magnetic contacts from the substrate lands.
    Type: Application
    Filed: December 28, 2012
    Publication date: July 3, 2014
    Inventors: Gregorio R. Murtagian, Bhanu Jaiswal, Sriram Srinivasan, Michael J. Hill