Patents by Inventor Bhanushankar Doni
Bhanushankar Doni has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 11960758Abstract: Rather than use one long folding operation to fold data from single-level cell (SLC) blocks into a multi-level cell (MLC) block, a storage system uses a multi-stage folding operation. By breaking up the folding process into stages, SLC blocks involved in an earlier stage can be released prior to a subsequent stage being performed. This can increase performance of the storage system by releasing SLC source blocks sooner and reducing an SLC block budget requirement.Type: GrantFiled: April 6, 2022Date of Patent: April 16, 2024Assignee: Western Digital Technologies, Inc.Inventors: Bhanushankar Doni Gurudath, Harish Gajula
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Publication number: 20240021249Abstract: Technology is disclosed herein for multi-stage data compaction. In a first data compaction stage valid data fragments from source erase block(s) are programmed into a destination erase block at two bits per memory cell. In a second data compaction stage additional valid data from the source erase block(s) is programmed into the destination erase block at two bits per memory cell. In this second stage, the same physical pages of memory cells in the destination erase block may be programmed such that each memory cell in the destination erase block is programmed to four bits.Type: ApplicationFiled: July 14, 2022Publication date: January 18, 2024Applicant: Western Digital Technologies, Inc.Inventors: Harish Gajula, Bhanushankar Doni
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Publication number: 20230325105Abstract: Rather than use one long folding operation to fold data from single-level cell (SLC) blocks into a multi-level cell (MLC) block, a storage system uses a multi-stage folding operation. By breaking up the folding process into stages, SLC blocks involved in an earlier stage can be released prior to a subsequent stage being performed. This can increase performance of the storage system by releasing SLC source blocks sooner and reducing an SLC block budget requirement.Type: ApplicationFiled: April 6, 2022Publication date: October 12, 2023Applicant: Western Digital Technologies, Inc.Inventors: Bhanushankar Doni Gurudath, Harish Gajula
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Patent number: 11714565Abstract: A data storage device, in one implementation, includes a memory device having Single Level Cell (SLC) blocks and Multi-Level Cell (MLC) blocks, such as Triple Level Cell (TLC) blocks. If a SLC block is determined to have errors, the SLC block is reallocated as a TLC block. In some implementations, the TLC block is used to store TLC cold data.Type: GrantFiled: November 18, 2021Date of Patent: August 1, 2023Assignee: Western Digital Technologies, Inc.Inventors: Bhanushankar Doni, Raghavendra Gopalkrishnan
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Patent number: 11698750Abstract: Technology is disclosed herein for efficient use of volatile memory that is used for accumulating parity data of user data being written to non-volatile memory cells. A memory controller may replace primary parity in a first portion of a parity buffer with data other than primary parity while a second portion of the buffer is still being used to store the primary parity. Therefore, the memory controller smartly re-uses the parity buffer, which makes efficient use of the volatile memory. In one aspect, a memory controller accumulates secondary parity for the user data in a first portion of the parity buffer while a second portion of the parity buffer is still being used to store the primary parity. The memory controller may compute the secondary parity from present content of the first portion of the parity buffer and primary parity presently stored in the second portion of the buffer.Type: GrantFiled: October 4, 2021Date of Patent: July 11, 2023Assignee: SanDisk Technologies LLCInventors: Bhanushankar Doni, Pratik Bhatt
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Publication number: 20230152995Abstract: A data storage device, in one implementation, includes a memory device having Single Level Cell (SLC) blocks and Multi-Level Cell (MLC) blocks, such as Triple Level Cell (TLC) blocks. If a SLC block is determined to have errors, the SLC block is reallocated as a TLC block. In some implementations, the TLC block is used to store TLC cold data.Type: ApplicationFiled: November 18, 2021Publication date: May 18, 2023Inventors: Bhanushankar Doni, Raghavendra Gopalkrishnan
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Publication number: 20230112636Abstract: Technology is disclosed herein for efficient use of volatile memory that is used for accumulating parity data of user data being written to non-volatile memory cells. A memory controller may replace primary parity in a first portion of a parity buffer with data other than primary parity while a second portion of the buffer is still being used to store the primary parity. Therefore, the memory controller smartly re-uses the parity buffer, which makes efficient use of the volatile memory. In one aspect, a memory controller accumulates secondary parity for the user data in a first portion of the parity buffer while a second portion of the parity buffer is still being used to store the primary parity. The memory controller may compute the secondary parity from present content of the first portion of the parity buffer and primary parity presently stored in the second portion of the buffer.Type: ApplicationFiled: October 4, 2021Publication date: April 13, 2023Applicant: SanDisk Technologies LLCInventors: Bhanushankar Doni, Pratik Bhatt
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Patent number: 11036582Abstract: An apparatus comprising non-volatile memory is configured to access a selected unit of encoded SLC data in the non-volatile memory during a first programming phase of a process of folding data stored at a single bit per memory cell to data stored at multiple bits per memory cell. The apparatus recovers the selected unit of SLC data based on redundancy data formed from units of SLC data that data include the selected unit of SLC data. The apparatus saves the recovered selected unit of SLC data to memory. The apparatus uses the saved recovered unit of SLC data during a second programming phase of folding the data stored at a single bit per memory cell to the data stored at multiple bits per memory cell, thereby saving considerable time in not having to again recover the SLC data using the redundancy data.Type: GrantFiled: September 27, 2019Date of Patent: June 15, 2021Assignee: Western Digital Technologies, Inc.Inventors: Raghavendra Gopalakrishnan, Bhanushankar Doni, Manohar Srinivasaiah
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Publication number: 20210096948Abstract: An apparatus comprising non-volatile memory is configured to access a selected unit of encoded SLC data in the non-volatile memory during a first programming phase of a process of folding data stored at a single bit per memory cell to data stored at multiple bits per memory cell. The apparatus recovers the selected unit of SLC data based on redundancy data formed from units of SLC data that data include the selected unit of SLC data. The apparatus saves the recovered selected unit of SLC data to memory. The apparatus uses the saved recovered unit of SLC data during a second programming phase of folding the data stored at a single bit per memory cell to the data stored at multiple bits per memory cell, thereby saving considerable time in not having to again recover the SLC data using the redundancy data.Type: ApplicationFiled: September 27, 2019Publication date: April 1, 2021Applicant: Western Digital Technologies, Inc.Inventors: Raghavendra Gopalakrishnan, Bhanushankar Doni, Manohar Srinivasaiah
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Patent number: 10635580Abstract: Apparatus, systems, methods, and computer program products for buffering storage device data in a host memory buffer (HMB) are presented. A non-volatile memory and a controller are in communication with a non-volatile memory. A controller is configured to receive an input/output (I/O) operation including data. A controller is configured to transmit at least a portion of data to an HMB of a host device separate from a non-volatile memory and a controller for storage until a trigger event occurs.Type: GrantFiled: July 9, 2018Date of Patent: April 28, 2020Assignee: Western Digital Technologies, Inc.Inventors: Kalpit Bordia, Raghavendra Gopalakrishnan, Sachin Krishna Kudva, Ashim Ranjan Saikia, Bhanushankar Doni Gurudath, Ramanathan Muthiah, Pradeep Sreedhar, Prashanth Reddy Enukonda, Ramkumar Ramamurthy
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Publication number: 20200012595Abstract: Apparatus, systems, methods, and computer program products for buffering storage device data in a host memory buffer (HMB) are presented. A non-volatile memory and a controller are in communication with a non-volatile memory. A controller is configured to receive an input/output (I/O) operation including data. A controller is configured to transmit at least a portion of data to an HMB of a host device separate from a non-volatile memory and a controller for storage until a trigger event occurs.Type: ApplicationFiled: July 9, 2018Publication date: January 9, 2020Applicant: Western Digital Technologies, Inc.Inventors: KALPIT BORDIA, RAGHAVENDRA GOPALAKRISHNAN, SACHIN KRISHNA KUDVA, ASHIM RANJAN SAIKIA, BHANUSHANKAR DONI GURUDATH, RAMANATHAN MUTHIAH, PRADEEP SREEDHAR, PRASHANTH REDDY ENUKONDA, RAMKUMAR RAMAMURTHY